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US 11,671,079 B1Granted
Systems and methods for concurrently driving clock pulse and clock pulse complement signals in latches of an application-specific integrated circuit
AssigneeBitmain Development Inc.
InventorsChristos Vezyrtzis, Peter Holm, Stephen M. Beccue
Life of this patent
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Abstract
Embodiments of the present invention provide for a core stage in an application-specific integrated circuit core which drives both a clock pulse signal and a clock pulse negative/complement signal concurrently, thereby resulting in perfectly aligned signals. The core stage can include a pulse generator, a clock distribution circuit, and a set of latches.
Claims11
An application-specific integrated circuit (ASIC) core, the ASIC core comprising:
- a plurality of core stages, each core stage comprising:
- a pulse generator, wherein the pulse generator is configured to (i) receive a clock pulse input and a plurality of digital inputs and (ii) generate a clock pulse output based on the received clock pulse input and the digital inputs;
- a clock distribution circuit, wherein the clock distribution circuit is configured to receive the clock pulse output and generate a clock pulse signal and a clock pulse complement signal concurrently based on the received clock pulse output;
- and
- a set of latches, wherein the set of latches is configured to receive the clock pulse signal and the clock pulse complement signal;
- wherein each of the pulse generators are connected in cascade and implement reverse and non-overlapping clock pulses.
3 more elements
Dependencies are inferred from the claim text.