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US 11,669,304 B2Granted
Arithmetic device and arithmetic circuit for performing multiplication and division
AssigneeKioxia Corporation
InventorMikio Shiraishi
Life of this patent
Estimating the term…
Abstract
According to one embodiment, an arithmetic device includes: a first input terminal; a second input terminal; an output terminal; a first logical shifter; a second logical shifter; a third logical shifter; a first AND gate; a second AND gate; a first multiplexer; a third AND gate; a first adder; a fourth logical shifter; a second multiplexer; a second adder; a first arithmetic shifter; a second arithmetic shifter; a third arithmetic shifter; a third multiplexer; a fourth multiplexer; and a fifth multiplexer.
Claims24
An arithmetic device including:
- a first input terminal configured to receive a first signal that transmits an input bit string;
- a second input terminal configured to receive a second signal that includes first to eighth control signals;
- an output terminal configured to output a signal indicating a product of a value indicated by the first signal and a value indicated by the second signal;
- a first logical shifter configured to output a first bit string obtained by shifting left a sequence of bits of the input bit string by one bit;
- a second logical shifter configured to output a second bit string obtained by shifting left a sequence of bits of the first bit string by one bit;
- a third logical shifter configured to output a third bit string obtained by shifting left a sequence of bits of the second bit string by one bit;
- a first AND gate configured to output a fourth bit string that is an arithmetic result of a logical product of values of the input bit string and the first control signal;
- a second AND gate configured to output a fifth bit string that is an arithmetic result of a logical product of values of the first bit string and the second control signal;
- a first multiplexer configured to output, based on the third control signal, a sixth bit string that is either the second bit string or the third bit string;
- a third AND gate configured to output a seventh bit string that is an arithmetic result of a logical product of values of the sixth bit string and the fourth control signal;
- a first adder configured to output an eighth bit string that is a sum of the seventh bit string and the fifth bit string;
- a fourth logical shifter configured to output a ninth bit string obtained by shifting left a sequence of bits of the eighth bit string by one bit;
- a second multiplexer configured to output, based on the fifth control signal, a tenth bit string that is either the eighth bit string or the ninth bit string;
- a second adder configured to output an eleventh bit string that is a sum of the fourth bit string and the tenth bit string;
- a first arithmetic shifter configured to output a twelfth bit string obtained by shifting right a sequence of bits of the eleventh bit string by five bits while maintaining a sign;
- a second arithmetic shifter configured to output a thirteenth bit string obtained by shifting right a sequence of bits of the twelfth bit string by one bit while maintaining a sign;
- a third arithmetic shifter configured to output a fourteenth bit string obtained by shifting right a sequence of bits of the thirteenth bit string by one bit while maintaining a sign;
- a third multiplexer configured to output, based on the sixth control signal, a fifteenth bit string that is either the eleventh bit string or the twelfth bit string;
- a fourth multiplexer configured to output, based on the seventh control signal, a sixteenth bit string that is either the thirteenth bit string or the fourteenth bit string;
- and
- a fifth multiplexer configured to output, as the signal indicating the product, an output signal that transmits either the fifteenth bit string or the sixteenth bit string based on the eighth control signal.
18 more elements
An arithmetic device comprising:
- a first input terminal configured to receive a first signal that transmits an input bit string;
- a second input terminal configured to receive a second signal that includes first to eighth control signals;
- an output terminal configured to output a signal indicating a product of a value indicated by the first signal and a value indicated by the second signal;
- a first logical shifter configured to output a first bit string obtained by shifting left a sequence of bits of the input bit string by one bit;
- a second logical shifter configured to output a second bit string obtained by shifting left a sequence of bits of the first bit string by one bit;
- a third logical shifter configured to output a third bit string obtained by shifting left a sequence of bits of the second bit string by one bit;
- a first AND gate configured to output a fourth bit string that is an arithmetic result of a logical product of values of the input bit string and the first control signal;
- a second AND gate configured to output a fifth bit string that is an arithmetic result of a logical product of values of the first bit string and the second control signal;
- a first multiplexer configured to output, based on the third control signal, a sixth bit string that is either the second bit string or the third bit string;
- a third AND gate configured to output a seventh bit string that is an arithmetic result of a logical product of values of the sixth bit string and the fourth control signal;
- a first adder configured to output an eighth bit string that is a sum of the seventh bit string and the fifth bit string;
- a fourth logical shifter configured to output a ninth bit string obtained by shifting left a sequence of bits of the eighth bit string by one bit;
- a second multiplexer configured to output, based on the fifth control signal, a tenth bit string that is either the eighth bit string or the ninth bit string;
- a second adder configured to output an eleventh bit string that is a sum of the fourth bit string and the tenth bit string;
- a first arithmetic shifter configured to output a twelfth bit string obtained by shifting right a sequence of bits of the eleventh bit string by five bits while maintaining a sign;
- a second arithmetic shifter configured to output a thirteenth bit string obtained by shifting right a sequence of bits of the twelfth bit string by one bit while maintaining a sign;
- a third arithmetic shifter configured to output a fourteenth bit string obtained by shifting right a sequence of bits of the thirteenth bit string by one bit while maintaining a sign;
- a third multiplexer configured to output, based on the sixth control signal, a fifteenth bit string that is either the eleventh bit string or the twelfth bit string;
- a fourth multiplexer configured to output, based on the seventh control signal, a sixteenth bit string that is either the thirteenth bit string or the fourteenth bit string;
- a fourth arithmetic shifter configured to output a seventeenth bit string obtained by shifting right a sequence of bits of the sixteenth bit string by six bits while maintaining a sign;
- an inverter configured to output an eighteenth bit string having a value obtained by inverting bits of the seventeenth bit string;
- an incrementer configured to output a nineteenth bit string having a sum of the eighteenth bit string and 1;
- a fifth multiplexer configured to output, based on the sixth control signal, a twentieth bit string that is either the seventeenth bit string or the nineteenth bit string;
- a third adder configured to output a twenty-first bit string that is a sum of the sixteenth bit string and the twentieth bit string;
- and
- a sixth multiplexer configured to output an output signal that transmits either the fifteenth bit string or the twenty-first bit string based on the eighth control signal.
23 more elements
An arithmetic device comprising:
- a first input terminal configured to receive a first signal that transmits an input bit string;
- a second input terminal configured to receive a second signal that includes first to eighth control signals;
- an output terminal configured to output a signal indicating a product of a value indicated by the first signal and a value indicated by the second signal;
- a first logical shifter configured to output a first bit string obtained by shifting left a sequence of bits of the input bit string by one bit;
- a second logical shifter configured to output a second bit string obtained by shifting left a sequence of bits of the first bit string by one bit;
- a third logical shifter configured to output a third bit string obtained by shifting left a sequence of bits of the second bit string by one bit;
- a first AND gate configured to output a fourth bit string that is an arithmetic result of a logical product of values of the input bit string and the first control signal;
- a second AND gate configured to output a fifth bit string that is an arithmetic result of a logical product of values of the first bit string and the second control signal;
- a first multiplexer configured to output, based on the third control signal, a sixth bit string that is either the second bit string or the third bit string;
- a third AND gate configured to output a seventh bit string that is an arithmetic result of a logical product of values of the sixth bit string and the fourth control signal;
- a first adder configured to output an eighth bit string that is a sum of the seventh bit string and the fifth bit string;
- a fourth logical shifter configured to output a ninth bit string obtained by shifting left a sequence of bits of the eighth bit string by one bit;
- a second multiplexer configured to output, based on the fifth control signal, a tenth bit string that is either the eighth bit string or the ninth bit string;
- a second adder configured to output an eleventh bit string that is a sum of the fourth bit string and the tenth bit string;
- a first arithmetic shifter configured to output a twelfth bit string obtained by shifting right a sequence of bits of the eleventh bit string by five bits while maintaining a sign;
- a second arithmetic shifter configured to output a thirteenth bit string obtained by shifting right a sequence of bits of the twelfth bit string by one bit while maintaining a sign;
- a third arithmetic shifter configured to output a fourteenth bit string obtained by shifting right a sequence of bits of the thirteenth bit string by one bit while maintaining a sign;
- a third multiplexer configured to output, based on the sixth control signal, a fifteenth bit string that is either the eleventh bit string or the twelfth bit string;
- a fourth multiplexer configured to output, based on the seventh control signal, a sixteenth bit string that is either the thirteenth bit string or the fourteenth bit string;
- a fourth arithmetic shifter configured to output a seventeenth bit string obtained by shifting right a sequence of bits of the sixteenth bit string by six bits while maintaining a sign;
- an inverter configured to output an eighteenth bit string having a value obtained by inverting bits of the seventeenth bit string;
- an incrementer configured to output a nineteenth bit string having a sum of the eighteenth bit string and 1;
- a fifth multiplexer configured to output, based on the sixth control signal, a twentieth bit string that is either the seventeenth bit string or the nineteenth bit string;
- a third adder configured to output a twenty-first bit string that is a sum of the sixteenth bit string and the twentieth bit string;
- a fifth arithmetic shifter configured to output a twenty-second bit string obtained by shifting right a sequence of bits of the twenty-first bit string by twelve bits while maintaining a sign;
- a fourth adder configured to output a twenty-third bit string that is a sum of the twenty-first bit string and the twenty-second bit string;
- and
- a sixth multiplexer configured to output, based on the eighth control signal, an output signal that transmits either the fifteenth bit string or the twenty-third bit string.
25 more elements
Dependencies are inferred from the claim text.