Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof

A device, comprising:

• a substrate;
• and
• an array of memory cells, each of the memory cells including:
• a first well in the substrate, the first well having a first surface;
• first and second doped regions in the first well adjacent to the first surface and separated from one another;
• a first gate insulator on the first surface of the first well and on the first and second doped regions in the first well;
• a selection gate on the first well;
• a second well in the substrate and spaced from the first well, the second well having a second surface coplanar with the first surface, the second well including third and fourth doped regions adjacent to the second surface and separated from one another;
• a second gate insulator on the second surface and on the third and fourth doped regions;
• an isolation region in the substrate between the first well and the second well, the isolation region spaced from the first well and the second well, the isolation region extending from the first surface toward the substrate, extending further into the substrate than the first and second well;
• and
• a floating gate extending from the first gate insulator to the second gate insulator.

A device, comprising:

• a substrate;
• a memory array in the substrate, the memory array including a plurality of EEPROM cells, the memory array having a first section and a second section, the first section of the plurality of EEPROM cells is each coupled to function as a ROM cell by a connection at a first metal level over the memory array, each EEPROM cell includes:
• a first well of a first type, the first well including three doped regions of a second type and a doped region of the first type;
• a second well of the first type, second first well including two doped regions of the second type and a doped region of the first type;
• an isolation region of a second type, the isolation region between and spaced from the first well and the second well;
• a buried well of the second type, the first and second well between the buried well and a first surface of the substrate, the isolation region extending between the first surface and the buried well;
• and
• a floating gate that is coupled to two of the doped regions of the second type in the first well and is coupled to the two doped regions of the second type in the first well.