US 11,662,981 B2 · Low-power programmable truncated multiplication circuitry

Abstract

Methods, apparatuses, and truncated multiplication circuitry for truncated multiplication are provided. Truncated multiplication circuitry includes a control register that includes a first section configured to store a first value representing truncating a most significant bit (MSB) of a partial product of a multiplier and a multiplicand, and a second section configured to store a value representing a truncation mode. The truncated multiplication circuitry also includes control circuitry configured to truncate the MSB of the partial product based on the truncation mode if the first section stores the first value. A method includes: in response to receiving a multiplier and a multiplicand, determining a partial product of the multiplier and the multiplicand; receiving a first value representing truncating a most significant bit (MSB) of the partial product and a value representing a truncation mode; and truncating the MSB of the partial product based on the truncation mode.

Claims20

Dependent claims

Truncated multiplication circuitry, comprising:

a control register comprising:
a first section configured to store a first value representing truncating a most significant bit (MSB) of a partial product of a multiplier and a multiplicand, and
a second section configured to store a value representing a first truncation mode or a value representing a second truncation mode;
and
control circuitry configured to:
truncate the MSB of the partial product based on the truncation mode if the first section stores the first value;
truncate a first-mode length of MSBs of the partial product if the second section stores the value representing the first truncation mode;
and
truncate a second-mode length of MSBs of the partial product if the second section stores the value representing the second truncation mode.

6 more elements

A non-transitory computer-readable storage medium storing a set of instructions that is executable by truncated multiplication circuitry to cause the truncated multiplication circuitry to perform a method, the method comprising:

in response to receiving a multiplier and a multiplicand, determining a partial product of the multiplier and the multiplicand;
receiving a first value representing truncating a most significant bit (MSB) of the partial product and a value representing a truncation mode;
and
truncating the MSB of the partial product based on the truncation mode, comprising:
if the truncation mode is a first truncation mode, truncating a first-mode length of MSBs of the partial product;
or
if the truncation mode is a second truncation mode, truncating a second-mode length of MSBs of the partial product.

4 more elements

Dependencies are inferred from the claim text.

Low-power programmable truncated multiplication circuitry

Life of this patent

Low-power programmable truncated multiplication circuitry

Life of this patent

Abstract

Claims20