Latency reduction in analog-to-digital converter-based receiver circuits

A method, comprising:

• generating an equalized signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols;
• sampling, by an activated subset of a plurality of analog-to-digital converter circuits using a recovered clock signal, the equalized signal during respective time periods to generate corresponding sets of samples, wherein a number of analog-to-digital converter circuits included in the activated subset is based on a baud rate of the serial data stream;
• generating a plurality of serialized sample streams that include samples from respective subsets of the activated subset of the plurality of analog-to-digital converter circuits, wherein a first serialized sample stream of the plurality of serialized sample streams includes first data corresponding to even-numbered data symbols of the plurality of data symbols, and wherein a second serialized sample stream of the plurality of serialized sample streams includes second data corresponding to odd-numbered data symbols of the plurality of data symbols;
• and
• generating, using the plurality of serialized sample streams, the recovered clock signal and a plurality of recovered data symbols.

An apparatus, comprising:

• a front-end circuit configured to generate an equalized signal using at least one signal that encodes a serial data stream that includes a plurality of data symbols;
• a sample circuit configured to:
• sample, using a recovered clock signal, the equalized signal to generate a plurality of samples;
• and
• re-time the plurality of samples to align a plurality of subsets of the plurality of samples with corresponding sample clock phases of a plurality of sample clock phases;
• a serializer circuit configured to generate a plurality of serialized sample streams that include respective ones of the plurality of subsets of the plurality of samples, wherein a first serialized sample stream of the plurality of serialized sample streams includes first data corresponding to even-numbered data symbols of the plurality of data symbols, and wherein a second serialized sample stream of the plurality of serialized sample streams includes second data corresponding to odd-numbered data symbols of the plurality of data symbols;
• and
• a recovery circuit configured to generate, using the plurality of serialized sample streams, the recovered clock signal and a plurality of recovered data symbols.