Magnetoelectric inverter
AssigneesBoard of Regents of the University of Nebraska, Intel Corporation, Board of Regents, The University of Texas System
InventorsNishtha Sharma Gaul, Andrew Marshall, Peter A. Dowben, Dmitri E. Nikonov
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Abstract
A magneto-electric (ME) inverter includes two anti-ferromagnetic spin orbit read (AFSOR) circuit elements, each AFSOR circuit element has a CMOS inverter; and an AFSOR device with a ME base layer; a semiconductor channel layer on the ME base layer and comprising a source terminal and a drain terminal, where the source terminal is coupled to an output of the CMOS inverter; and a gate electrode on the semiconductor channel layer. The gate electrode of a second AFSOR device of the two AFSOR circuit elements is coupled to the drain terminal of a first AFSOR device of the two AFSOR circuit elements.
Claims6
A magneto-electric (ME) inverter, comprising:
- two anti-ferromagnetic spin orbit read (AFSOR) circuit elements, each AFSOR circuit element comprising:
- a CMOS inverter;
- and
- an AFSOR device comprising:
- a ME base layer;
- a semiconductor channel layer on the ME base layer and comprising a source terminal and a drain terminal, wherein the source terminal is coupled to an output of the CMOS inverter;
- and
- a gate electrode on the semiconductor channel layer,
- wherein the gate electrode of a second AFSOR device of the two AFSOR circuit elements is coupled to the drain terminal of a first AFSOR device of the two AFSOR circuit elements.
A non-transitory computer-readable storage medium having stored thereon a cell library, the cell library comprising instructions for representing and optionally simulating devices when executed by a computing device, cells of the cell library comprising:
- a magneto-electric (ME) inverter, comprising:
- two anti-ferromagnetic spin orbit read (AFSOR) circuit elements, each AFSOR circuit element comprising:
- a CMOS inverter;
- and
- an AFSOR device comprising:
- a ME base layer;
- a semiconductor channel layer on the ME base layer and comprising a source terminal and a drain terminal, wherein the source terminal is coupled to an output of the CMOS inverter;
- and
- a gate electrode on the semiconductor channel layer,
- wherein the gate electrode of a second AFSOR device of the two AFSOR circuit elements is coupled to the drain terminal of a first AFSOR device of the two AFSOR circuit elements.
Dependencies are inferred from the claim text.