US 11,658,481 B1Granted

Source and drain enabled conduction triggers and immunity tolerance for integrated circuits

AssigneeAmplexia, LLC

InventorStephen R. Fairbanks

Life of this patent

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Abstract

Integrated circuits with enhanced EOS/ESD robustness and methods of designing same. One such integrated circuit includes a plurality of input/output pads, a positive voltage rail, a ground voltage rail, a collection of internal circuits representing the operational core of the integrated circuit, a plurality of input/output buffering circuits connected as inputs and outputs to the internal circuits, wherein the internal circuits and the input/output buffering circuits comprise functional devices, and a plurality of EOS/ESD protection circuits interconnected with the input/output pads to limit ESD voltage and/or shunt ESD current away from the functional devices. At least one of the EOS/ESD protection circuits is a MOSFET. The MOSFET has a source region having an accompanying ohmic contact. The MOSFET further has a rectifying junction contact in place of a drain region and accompanying ohmic contact.

Claims17

Dependent claims

A method of designing an integrated circuit with enhanced EOS/ESD robustness, comprising the steps of:

(a) designing a plurality of input/output pads in the integrated circuit;
(b) designing a positive voltage rail in the integrated circuit;
(c) designing a ground voltage rail in the integrated circuit;
(d) designing a collection of internal circuits, in the integrated circuit, representing the operational core of the integrated circuit in the integrated circuit;
(e) designing a plurality of input/output buffering circuits, in the integrated circuit, connected as inputs and outputs to the internal circuits, wherein the internal circuits and the input/output buffering circuits comprise functional devices;
and
(f) designing a plurality of EOS/ESD protection circuits, in the integrated circuit, interconnected with the input/output pads to limit ESD voltage and/or shunt ESD current away from the functional devices, wherein at least one of the EOS/ESD protection circuits is a MOSFET;
(g) wherein designing the MOSFET includes designing a source region of the MOSFET to have an accompanying ohmic contact and designing the MOSFET to have a rectifying junction contact in place of a drain region and accompanying ohmic contact of the MOSFET;
and
(h) wherein the at least one EOS/ESD protection circuit has a first I-V characterization curve having a first snapback voltage, wherein at least one of the functional devices has a second I-V characterization curve having a second snapback voltage, and wherein the rectifying junction contact in the at least one EOS/ESD protection circuit causes the first snapback voltage to be less than the second snapback voltage.

7 more elements

A method of designing an integrated circuit with enhanced EOS/ESD robustness, comprising the steps of:

(a) designing a plurality of input/output pads in the integrated circuit;
(b) designing a positive voltage rail in the integrated circuit;
(c) designing a ground voltage rail in the integrated circuit;
(d) designing a collection of internal circuits, in the integrated circuit, representing the operational core of the integrated circuit;
(e) designing a plurality of input/output buffering circuits, in the integrated circuit, connected as inputs and outputs to the internal circuits, wherein the internal circuits and the input/output buffering circuits comprise functional devices;
and
(f) designing a plurality of EOS/ESD protection circuits, in the integrated circuit, interconnected with the input/output pads to limit ESD voltage and/or shunt ESD current away from the functional devices, wherein at least one of the EOS/ESD protection circuits is a bipolar junction transistor (BJT);
(g) wherein designing the BJT includes designing an emitter region of the BJT to have an accompanying ohmic contact and designing the BJT to have a rectifying junction contact in place of a collector region and accompanying ohmic contact;
and
(h) wherein the at least one EOS/ESD protection circuit has a first I-V characterization curve having a first snapback voltage, wherein at least one of the functional devices has a second I-V characterization curve having a second snapback voltage, and wherein the rectifying junction contact in the at least one EOS/ESD protection circuit causes the first snapback voltage to be less than the second snapback voltage.

7 more elements

A method of designing an integrated circuit with enhanced EOS/ESD robustness, comprising the steps of:

(a) designing a plurality of input/output pads in the integrated circuit;
(b) designing a positive voltage rail in the integrated circuit;
(c) designing a ground voltage rail in the integrated circuit;
(d) designing a collection of internal circuits, in the integrated circuit, representing the operational core of the integrated circuit;
(e) designing a plurality of input/output buffering circuits, in the integrated circuit, connected as inputs and outputs to the internal circuits, wherein the internal circuits and the input/output buffering circuits comprise functional devices, and wherein at least one of the functional devices includes a bipolar junction transistor (BJT);
and
(f) designing a plurality of EOS/ESD protection circuits, in the integrated circuit, interconnected with the input/output pads to limit ESD voltage and/or shunt ESD current away from the functional devices;
(g) wherein designing the BJT includes designing a collector region of the BJT to have an accompanying ohmic contact and designing the BJT to have a rectifying junction contact in place of an emitter region and accompanying ohmic contact;
and
(h) wherein the at least one functional device has a first I-V characterization curve having a first snapback current, wherein at least one of the EOS/ESD protection circuits has a second I-V characterization curve having a second snapback current, and wherein the rectifying junction contact in the at least one functional device causes the first snapback current to be greater than the second snapback current.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/576,267Filed 14 Jan 2022 · continuation
Priority: 30 May 2019
Granted: 23 May 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H02H 9/046
Adapted to a particular application and not provided for elsewhere: responsive to excess voltage appearing at terminals of integrated circuits
H10D 89/813
Using FETs as protective elements: specially adapted to provide an electrical current path other than the field-effect induced current path
H10D 89/713
Using bipolar transistors as protective elements: including a PNP transistor and a NPN transistor, wherein each of said transistors has its base…
H10D 89/811
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using FETs as protective elements