Dual row select pixel for fast pixel binning

An imaging system, comprising:

• a pixel array, including:
• a plurality of pixel cells arranged into rows and columns, wherein each of the pixel cells is configured to generate a respective image signal in response to incident light, wherein each of the pixel cells includes:
• a plurality of photodiodes configured to generate image charge in response to the incident light;
• a first floating diffusion coupled to receive the image charge generated by the plurality of photodiodes;
• a source follower transistor coupled to the first floating diffusion to generate the respective image signal in response to the image charge in the first floating diffusion;
• and
• a first row select transistor coupled to the source follower transistor to output the respective image signal of said each of the pixel cells;
• and
• a plurality of column bitlines including a first column bitline and a second column bitline, wherein the first column bitline is a single bitline and the second column bitline is a single bitline, wherein the pixel cells are organized into columns of pixel cells including a first column and a second column, wherein each of the first row select transistors of the pixel cells in the first column is coupled to the first column bitline, wherein each of the first row select transistors of the pixel cells in the second column is coupled to the second column bitline, and
• wherein a second pixel cell of a first row of the pixel array in the second column further comprises a second row select transistor coupled to the source follower transistor of the second pixel cell to output the respective image signal of said second pixel cell in the first row of the pixel array in the second column,
• wherein a first pixel cell in the first row of the pixel array in the first column further comprises a second row select transistor coupled to the source follower transistor of the first pixel cell to output the respective image signal of said first pixel cell in the first row of the pixel array in the first column, wherein the second row select transistor of the first pixel cell in the first row of the pixel array in the first column and the second row select transistor of the second pixel cell in the first row of the pixel array in the second column are both directly coupled to a same one of the first column bitline or the second column bitline,
• wherein a fourth pixel cell of a second row of the pixel array in the second column further comprises a second row select transistor coupled to a source follower transistor of the fourth pixel cell to output the respective image signal of said fourth pixel cell in the second row of the pixel array in the second column, and
• wherein a third pixel cell in the second row of the pixel array in the first column further comprises a second row select transistor coupled to a source follower transistor of the third pixel cell to output the respective image signal of said third pixel cell in the second row of the pixel array in the first column, wherein the second row select transistor of the third pixel cell in the second row of the pixel array in the first column and the second row select transistor of the fourth pixel cell in the second row of the pixel array in the second column are both directly coupled to a same other one of the first column bitline or the second column bitline;
• control circuitry coupled to the pixel array to control operation of the pixel array;
• and
• readout circuitry coupled to the pixel array to readout image data from the pixel array.