Phase coherent frequency synthesis

A phase coherent fractional-N phase locked loop (PLL) device comprising:

• a fractional-N PLL circuit;
• a coherent phase generator circuit coupled to the fractional-N PLL circuit comprising:
• a first phase accumulator configured to accumulate a fractional divide control word in response to a reference clock signal to produce a first digital phase signal;
• a second phase accumulator configured to produce an incrementing reference count in response to the reference clock signal and configured to multiply the incrementing reference count by the fractional divide control word, the multiplication performed in response to detection of a change in the fractional divide control word, to produce a second digital phase signal;
• and
• a multiplexer configured to provide the second digital phase signal as a selected digital phase signal in response to detected completion of the multiply, otherwise to provide the first digital phase signal as the selected digital phase signal;
• and
• an overflow detection circuit coupled to the coherent phase generator circuit and configured to generate a carry bit based on detection of an overflow of the selected digital phase signal, the carry bit to control fractional switching of the fractional-N PLL circuit to maintain phase coherence between output signals of the fractional-N PLL circuit, alternating between a first output frequency and a second output frequency.