Layout design of dual row select structure

An imaging system, comprising:

• a pixel array, including:
• a plurality of pixel cells disposed in a semiconductor material, wherein each of the pixel cells of the plurality of pixel cells includes:
• a plurality of photodiodes to generate image charge in response to incident light;
• a first floating diffusion coupled to receive the image charge generated by the plurality of photodiodes;
• a first source follower transistor having a gate coupled to the first floating diffusion to generate a respective image signal at a source region of the first source follower transistor in response to the image charge in the first floating diffusion;
• and
• a first row select transistor having a drain region coupled to the source region of the first source follower;
• a second row select transistor having a drain region coupled to the source region of the first source follower;
• and
• a common junction disposed in the semiconductor material between a gate of the first row select transistor and a gate of the second row select transistor, wherein the drain region of the first row select transistor and the drain region of the second row select transistor are shared and coupled together through the semiconductor material of the common junction;
• and
• a plurality of column bitlines coupled to the plurality of pixel cells, wherein the plurality of pixel cells are organized into a plurality of columns of pixel cells and a plurality of rows of pixel cells, wherein each one of the plurality of column bitlines corresponds to a respective one of the plurality of columns of pixel cells;
• control circuitry coupled to the pixel array to control operation of the pixel array;
• and
• readout circuitry coupled to the pixel array to readout image data from the pixel array.