Image sensor with delta sigma modulators and shared filters
AssigneeSemiconductor Components Industries, LLC
InventorCarl Luypaert
Life of this patent
Estimating the term…
Abstract
An image sensor may include an array of image pixels arranged in rows and columns. The columns of pixels are coupled to corresponding delta sigma modulators. Each group of delta sigma modulators may be coupled to a column memory circuit. The column memory circuit may receive bits serially from each pixel column in the group. Once all bits in a bit stream from each pixel column have been stored into the column memory circuit, the column memory circuit may output one bit stream at a time to a shared filter circuit. The shared filter circuit may process an entire bit stream associated with a given column in one cycle. Sharing the filter circuit among multiple pixel columns can dramatically reduce circuit area for the image sensor.
Claims20
An image sensor, comprising:
- a first column of pixels;
- a second column of pixels;
- a first data converter configured to receive a signal from the first column of pixels;
- a second data converter configured to receive a signal from the second column of pixels;
- a column memory circuit configured to store bits generated by the first data converter and to store bits generated by the second data converter;
- and
- a filter circuit coupled to the column memory circuitry and shared among at least the first data converter and the second data converter.
A method of operating an image sensor, comprising:
- reading a signal from a first column of pixels;
- reading a signal from a second column of pixels;
- with a first data converter, receiving the signal from the first column of pixels;
- with a second data converter, receiving the signal from the second column of pixels;
- with column memory, storing serial bits output from the first data converter and storing serial bits output from the second data converter;
- with the column memory, outputting the stored bits from the first data converter in parallel to a filter circuit during a first time period;
- and
- with the column memory, outputting the stored bits from the second data converter in parallel to the filter circuit during a second time period after the first time period.
An apparatus comprising:
- a first pixel output line;
- a second pixel output line;
- a first analog-to-digital converter having an input coupled to the first pixel output line and having an output;
- a second analog-to-digital converter having an input coupled to the second pixel output line and having an output;
- a column memory circuit having a first input coupled to the output of the first analog-to-digital converter, a second input coupled to the output of the second analog-to-digital converter, and a parallel output;
- and
- a filter circuit having an input coupled to the parallel output and having an output on which a digital value is generated.
Dependencies are inferred from the claim text.