Fractional time delay structures in digitally oversampled microphone systems, circuits, and methods

A fractional delay block to time delay an oversampled digital signal, comprising:

• a first inverter, the first inverter has a first input and a first output;
• a second inverter, the second inverter has a second input and a second output, the first output is connected to the second input to form a first pair of inverters;
• a third inverter, the third inverter has a third input and a third output;
• a fourth inverter, the fourth inverter has a fourth input and a fourth output, the third output is connected to the fourth input to form a second pair of inverters;
• the second output is connected to the third input to form a first paired inverter group;
• and
• the fractional delay block is configured to receive the oversampled digital signal from an oversampled sensor and to provide the oversampled digital signal to the first input, in operation the oversampled digital signal is available on the fourth output and is delayed in time by a propagation time through the first paired inverter group.

A method to select a sub-fractional time delay to time delay an oversampled digital signal, comprising:

• specifying a set of sampling clock frequencies;
• determining a minimum time delay value based on the set of sampling clock frequencies, wherein a minimum time delay value is a sub-fractional time delay for the set of sampling clock frequencies;
• and
• establishing a least significant common number of grouped pairs of inverters required to provide the minimum time delay value.

A non-transitory computer-readable medium storing program code for causing a data processing system to perform the steps comprising:

• receiving a time delayed output from a fractional delay block in an oversampled sensor, wherein a first time delay was imparted to the time delayed output in an oversampled domain;
• processing the time delayed output through a pulse density modulation receiver to produce a down sampled output;
• and
• applying a second time delay to the down sampled output, wherein a total time delay applied relative to the oversampled domain is a sum of the first time delay and the second time delay.

A processor module to communicate with an oversampled sensor, comprising:

• a data processing system, the data processing system is configured to process acoustic signals received from the oversampled sensor;
• and
• a non-transitory computer readable medium containing executable computer program instructions, which when executed by the data processing system, cause the data processing system to perform steps comprising:
• receiving a time delayed output from a fractional delay block in the oversampled sensor, wherein a first time delay was imparted to the time delayed output in an oversampled domain;
• processing the time delayed output through a pulse density modulation receiver to produce a down sampled output;
• and
• applying a second time delay to the down sampled output, wherein a total time delay applied to the acoustic signals is a sum of the first time delay and the second time delay.