US 11,645,155 B2 · Safe-stating a system interconnect within a data processing system

Abstract

A data processing system includes a system interconnect, a first master, and a bridge circuit. The bridge circuit is coupled between the first master and the system interconnect. The bridge circuit is configured to, in response to occurrence of an error in the first master, isolate the first master from the system interconnect, wherein the isolating by the bridge circuit is performed while the first master has one or more outstanding issued write commands to the system interconnect which have not been completed. The bridge circuit is further configured to, after isolating the first master from the system interconnect, complete the one or more outstanding issued write commands while the first master remains isolated from the system interconnect.

Claims18

Dependent claims

A data processing system, comprising:

a system interconnect;
a first master;
a bridge circuit coupled between the first master and the system interconnect, wherein the bridge circuit is configured to:
in response to occurrence of an error in the first master, isolate the first master from the system interconnect, wherein the isolating by the bridge circuit is performed while the first master has one or more outstanding issued write commands to the system interconnect which have not been completed, and
after isolating the first master from the system interconnect, complete the one or more outstanding issued write commands while the first master remains isolated from the system interconnect, wherein the bridge circuit is configured to complete the one or more outstanding issued write commands by providing dummy data to the system interconnect for each of the one or more outstanding write commands, wherein each dummy data includes a negated strobe signal.

2 more elements

In a data processing system having a first master, a system interconnect, and a bridge circuit coupled between the first master and the system interconnect, a method comprising:

issuing, by the first master, write commands and write data to the system interconnect via the bridge circuit wherein prior to occurrence of an error in the first master, the write commands and write data are provided unmodified to the system interconnect by the bridge circuit;
and tracking, by the bridge circuit, issued write commands which have not been completed as outstanding write commands, wherein, after occurrence of the error in the first master, the bridge circuit isolates the first master from the system interconnect and completes the outstanding write commands while the first master remains isolated from the system interconnect, wherein, after occurrence of the error in the first master, the bridge circuit completes the outstanding write commands by providing dummy data corresponding to each outstanding write command to the system interconnect so as to receive a corresponding valid response from the system interconnect to complete each outstanding write command.

Dependencies are inferred from the claim text.

Safe-stating a system interconnect within a data processing system

Life of this patent

Safe-stating a system interconnect within a data processing system

Life of this patent

Abstract

Claims18