Parallel hardware hypervisor for virtualizing application-specific supercomputers

A hypervisor system for virtualizing application-specific supercomputers, the hypervisor system comprising:

• (a) at least one software-virtual hardware pair consisting of a software application, and an application-specific virtual supercomputer for accelerating the software application, where:
• i. the application-specific virtual supercomputer comprises a plurality of virtual tiles;
• and
• ii. communication messages are sent and received between both the software application and the plurality of virtual tiles;
• (b) a plurality of reconfigurable physical tiles, where each virtual tile of the plurality of virtual tiles of the application-specific virtual supercomputer can be implemented on at least one reconfigurable physical tile, by configuring the reconfigurable physical tile to perform a function of the virtual tile;
• and
• (c) a scheduler implemented in hardware, for parallel pre-emptive scheduling of the plurality of virtual tiles on the reconfigurable physical tiles;
• where the scheduler is separate from the reconfigurable physical tiles;
• and where the scheduler simultaneously performs a plurality of pre-emptive scheduling actions, where a pre-emptive scheduling action of the plurality of pre-emptive scheduling actions comprises pre-empting a virtual tile operating on a reconfigurable physical tile, letting the pre-empted virtual tile remain pre-empted for a period of time, and then resuming operation of the pre-empted virtual tile on a possibly different reconfigurable physical tile;
• and where the virtual tile retains ability to receive a message when pre-empted;
• and
• where in at least one software-virtual hardware pair of (a), consisting of the software application and the application-specific virtual supercomputer for accelerating the software application:
• the software application is an entire operating system, including user applications;
• and the virtual tiles of the application-specific virtual supercomputer comprises:
• special-purpose hardware for accelerating critical kernel and user code fragments of the entire operating system;
• and
• a general-purpose processor for accelerating remaining, non-critical code fragments of the entire operating system.