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US 11,644,501 B2Granted
Method for identifying PCB core-layer properties
AssigneeInternational Business Machines Corporation
InventorsTao Song, Zhongfeng Yang, XiYuan Yin, Xiao Hu, LiCen Mu, Mingman Li
Life of this patent
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Abstract
A reference via in a set of plated vias on a printed circuit board is located. A reference lead is applied to the reference via. A test via in the set of plated vias is located. A test lead is applied to the test via. An electrical conductance between the reference via and the test via is measured. A property of a core layer of the printed circuit board is identified based on the electrical conductance.
Claims20
A method comprising:
- locating a first reference via in a first set of plated vias on a printed circuit board;
- applying a reference lead to the first reference via;
- locating a first test via in the first set of plated vias;
- applying a test lead to the first test via;
- measuring a first electrical conductance between the first reference via and the first test via;
- and
- recording the first electrical conductance as a first value in a core lot code, wherein the core lot code reflects a first property of a first core layer of the printed circuit board.
4 more elements
A printed circuit board comprising:
- a set of core layers;
- a set of reference vias;
- and
- a set of core codes, wherein each core code corresponds to a core layer in the set of core layers, and wherein each core code comprises a set of test vias;
- wherein a pattern of electrical connections between the set of test vias in a particular core code and a particular reference via in the set of reference vias signifies a property of the particular core layer to which the particular core code corresponds.
2 more elements
A method of making a printed circuit board, comprising:
- forming a first core layer;
- creating a first reference location on the first core layer;
- creating a first test location on the first core layer;
- forming an electrical connection between the first reference location and the first test location;
- laminating the printed circuit board;
- drilling a first reference via through the printed circuit board at the first reference location;
- drilling a first test via through the printed circuit board at the first test location;
- plating the first reference via and the first test via;
- and
- generating a core lot code that corresponds to the electrical connection, wherein the core lot code reflects a first property of a first core layer of the printed circuit board.
7 more elements
Dependencies are inferred from the claim text.