Three-dimensional memory device with peripheral circuit located over support pillar array and method of making thereof

A method of forming a three-dimensional memory device, comprising:

• forming a memory-level assembly over a substrate, wherein the memory-level assembly comprises a first alternating stack of first insulating layers and first electrically conductive layers, memory stack structures vertically extending through the first alternating stack, and a second alternating stack of second insulating layers and second electrically conductive layers, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;
• forming a contact-level dielectric layer over the first alternating stack and the second alternating stack;
• bonding a planar semiconductor material layer to the contact-level dielectric layer;
• forming field effect transistors on the planar semiconductor material layer;
• and
• forming interconnect-level dielectric material layers embedding metal interconnect structures over the field effect transistors, wherein the metal interconnect structures provide electrical connection between the field effect transistors and the first electrically conductive layers.

A method of forming a three-dimensional memory device, comprising:

• forming a memory-level assembly over a substrate, wherein the memory-level assembly comprises a first alternating stack of first insulating layers and first electrically conductive layers, memory stack structures vertically extending through the first alternating stack, and a second alternating stack of second insulating layers and second electrically conductive layers, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;
• forming a contact-level dielectric layer over the first alternating stack and the second alternating stack;
• bonding a planar semiconductor material layer to the contact-level dielectric layer;
• and
• forming field effect transistors on the planar semiconductor material layer;
• wherein:
• the first alternating stack comprises first stepped surfaces;
• the second alternating stack comprises second stepped surfaces;
• and
• the memory-level assembly comprises a retro-stepped dielectric material portion located between the first alternating stack and the second alternating stack and contacting the first stepped surfaces and the second stepped surfaces;
• and
• further comprising forming word line contact via structures through the retro-stepped dielectric material portion directly on a respective one of the first electrically conductive layers prior to bonding the planar semiconductor material layer;
• wherein:
• the first stepped surfaces rise at a steeper angle from the substrate than the second stepped surfaces;
• the second electrically conductive layers are electrically floating and not electrically connected to a driver circuit;
• and
• the second electrically conductive layers are not electrically contacted by any of the word line contact via structures which vertically extend through the retro-stepped dielectric material portion.