Embedded sonos with a high-K metal gate and manufacturing methods of the same

A memory device, comprising:

• a substrate disposed within a single semiconductor die;
• a plurality of non-volatile memory (NVM) transistors formed in a first region of the substrate, wherein at least one NVM transistor comprises a blocking dielectric including a first high dielectric constant (high-K) dielectric layer overlying a blocking oxide having a blocking oxide thickness and a first vertical sidewall spacer that directly contacts the blocking dielectric;
• and
• a plurality of metal-oxide-semiconductor (MOS) transistors formed in a second region of the substrate, wherein the plurality of MOS transistors include a high voltage (HV) MOS transistor, an input/output (I/O) MOS transistor, and a low voltage (LV) MOS transistor, a gate dielectric layer of the I/O MOS, and LV MOS transistors having distinctively different thicknesses from the HV MOS transistor, and each gate dielectric layer of the HV MOS, I/O MOS, and LV MOS transistors are with the same dielectric materials, wherein a gap between the first vertical sidewall spacer of the at least one NVM transistor and a second vertical sidewall spacer of a MOS transistor of the plurality of MOS transistors that directly contacts a first gate dielectric of the MOS transistor and a second gate dielectric of the MOS transistor separates the first region of the substrate from the second region of the substrate;
• wherein the at least one NVM transistor comprises a charge-trapping layer, the charge-trapping layer comprising a first charge-trapping layer that is oxygen-rich and a second charge-trapping layer disposed over the first charge-trapping layer that is silicon-rich and oxygen-lean relative to the first charge-trapping layer, wherein a thin oxide layer formed between the first and second charge-trapping layers;
• and
• wherein each gate dielectric layer of the I/O MOS, LV MOS, and HV MOS transistors comprises a second high-K dielectric layer, and the first and second high-K dielectric layers comprise the exact same material and the exact same thickness.

A semiconductor system, comprising:

• a system-on-chip (SOC) device;
• a plurality of logic devices, wherein the SOC device and the plurality of logic devices are in a second region;
• and
• an embedded non-volatile memory (NVM) device disposed within one single semiconductor die in a first region, wherein the embedded NVM comprises a first vertical sidewall spacer that directly contacts a tunnel dielectric layer, a charge-trapping layer, and a blocking dielectric layer of the embedded NVM, and a gap between the first vertical sidewall spacer of the NVM device and a second vertical sidewall spacer of one of the SOC device and the plurality of logic devices separates the first region of the semiconductor system from the second region of the semiconductor system, wherein the second vertical sidewall spacer directly contacts a first gate dielectric and a second gate dielectric one of the SOC device and the plurality of logic devices, and wherein:
• the embedded NVM device includes a plurality of metal-oxide-nitride-oxide-semiconductor (MONOS) transistors, where at least one MONOS transistor includes a first metal gate layer overlying a blocking dielectric including a first high dielectric constant (high-K) dielectric layer disposed overlying a blocking oxide having a blocking oxide thickness;
• and
• the SOC device and the plurality of logic devices include high voltage (HV) metal-oxide-semiconductor (MOS) transistors, input/output (I/O) MOS transistors, and low voltage (LV) MOS transistors, wherein gate dielectric of each of the HV MOS, I/O MOS, and LV MOS transistors includes a second high-K dielectric layer, and wherein the gate dielectric of the HV MOS transistors are thicker than the gate dielectric of the I/O MOS transistors, and the gate dielectric of the I/O MOS transistors are thicker than the gate dielectric of the LV MOS transistors, wherein the gate dielectric of the LV MOS transistors include nitrided silicon oxide, and wherein a portion of the blocking oxide and a portion of the gate dielectric of the HV MOS transistors are formed simultaneously such that the blocking oxide thickness is corresponding to thickness of the gate dielectric of the HV MOS transistors;
• wherein the embedded NVM device comprises the charge-trapping layer, the charge-trapping layer comprising a first charge-trapping layer that is oxygen-rich and a second charge-trapping layer disposed over the first charge-trapping layer that is silicon-rich and oxygen-lean relative to the first charge-trapping layer, wherein a thin oxide layer formed between the first and second charge-trapping layers;
• and
• wherein each gate dielectric layer of the I/O MOS, LV MOS, and HV MOS transistors comprises a second high-K dielectric layer, and the first and second high-K dielectric layers comprise the exact same material and the exact same thickness.