Semiconductor non-volatile memory devices

A memory device comprising:

• a substrate having a first active region and a second active region laterally spaced from the first active region;
• an isolation region between the first active region and the second active region;
• a first electrically-isolated electrode over the first active region, wherein the first electrically-isolated electrode has a first portion of a first electrode thickness and a second portion of a second electrode thickness that is greater than the first electrode thickness, and the first portion and the second portion have substantially coplanar upper surfaces;
• a second electrically-isolated electrode over the second active region, wherein the second electrically-isolated electrode has an electrode thickness equal to the second electrode thickness of the first electrically-isolated electrode and forms a floating gate with the first electrically-isolated electrode for the memory device;
• and
• a dielectric layer directly under the first electrically-isolated electrode and the second electrically-isolated electrode, wherein the dielectric layer has a first dielectric portion having a first dielectric thickness directly under the first portion of the first electrically-isolated electrode and a second dielectric portion having a second dielectric thickness directly under the second portion of the first electrically-isolated electrode and the second electrically-isolated electrode, the second dielectric thickness is thinner than the first dielectric thickness.