US 11,641,738 B2Granted

Three-dimensional semiconductor memory device

AssigneeSamsung Electronics Co., Ltd.

InventorsWoosung Yang, Byungjin Lee, Bumkyu Kang, Dong-Sik Lee

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Abstract

A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

Claims20

Dependent claims

A three-dimensional semiconductor memory device, comprising:

a first peripheral circuit including a plurality of different decoder circuits;
a first memory on the first peripheral circuit, the first memory including
a first stack structure having a plurality of first electrode layers stacked on one another and a plurality of first inter-electrode dielectric layers between first electrode layers of the plurality of first electrode layers,
a first planarized dielectric layer covering an end of the first stack structure, and
a first through via that penetrates the first planarized dielectric layer and the end of the first stack structure, the first through via being insulated from the plurality of first electrode layers and electrically connected to one of the plurality of different decoder circuits;
and
a second memory on the first memory, the second memory including
a second stack structure having a plurality of second electrode layers stacked on one another and a plurality of second inter-electrode dielectric layers between second electrode layers of the plurality of second electrode layers,
a second planarized dielectric layer covering an end of the second stack structure, and
a first cell contact plug that penetrates the second planarized dielectric layer, the first cell contact plug electrically connecting one of the plurality of second electrode layers to the first through via.

7 more elements

A three-dimensional semiconductor memory device, comprising:

a peripheral circuit including a plurality of different decoder circuits;
a first memory on the peripheral circuit, the first memory including a first stack structure and a second stack structure spaced apart from each other in a first direction parallel to a top surface of the peripheral circuit, the first stack structure including a plurality of first electrode layers stacked on one another, the plurality of first electrode layers being electrically connected to a first decoder circuit among the plurality of different decoder circuits, and the second stack structure including a plurality of second electrode layers stacked on one another;
and
a second memory on the first memory, the second memory including a third stack structure and a fourth stack structure spaced apart from each other in the first direction, the third stack structure including a plurality of third electrode layers stacked on one another, the plurality of third electrode layers being electrically connected to a second decoder circuit among the plurality of different decoder circuits, and the fourth stack structure including a plurality of fourth electrode layers stacked on one another.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 17/021,416Filed 15 Sep 2020
Priority: KR 10-2020-000535015 Jan 2020
Published: US 2021/0217760 A115 Jul 2021
Granted: 2 May 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10B 41/46
Comprising only one type of peripheral transistor: with an inter-gate dielectric layer also being used as part of the peripheral transistor
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout