Manufacturing method of static random access memory cell

A method for manufacturing a static random access memory (SRAM) cell comprising:

• forming a first p-well and a second p-well spaced from the first p-well by an n-well in a semiconductor substrate;
• forming a first semiconductor fin extending within the first p-well and a second semiconductor fin extending within the second p-well;
• doping the first and second semiconductor fins with a first dopant;
• after doping the first and second semiconductor fins, forming a mask layer over the first and second semiconductor fins;
• patterning the mask layer to expose the first semiconductor fin, while leaving the second semiconductor fin covered by the mask layer;
• with the patterned mask layer in place, doping the first semiconductor fin with a second dopant;
• after doping the first semiconductor fin, removing the mask layer from the second semiconductor fin;
• and
• forming a first gate structure extending across the first semiconductor fin, which has the first dopant and the second dopant, to form a first pull-down transistor, and forming a second gate structure extending across the second semiconductor fin, which has the first dopant, to form a second pull-down transistor, wherein the first pull-down transistor has a threshold voltage same as a threshold voltage of the second pull-down transistor.

A method for manufacturing a static random access memory (SRAM) cell comprising:

• forming a first p-well within a write portion and a read portion within a semiconductor substrate;
• forming a second p-well within the write portion and spaced apart from the first p-well;
• forming a first semiconductor fin extending within the first p-well within the write portion, and a second semiconductor fin extending within the first p-well within the read portion, and a third semiconductor fin within the second p-well;
• forming a first mask layer covering the second semiconductor fin, while leaving the first semiconductor fin exposed;
• with the first mask layer in place, doping a first channel region of the first semiconductor fin with a first dopant to form a first channel doping layer, wherein the first channel region is a channel region of a first write-port pull-down transistor of the SRAM cell;
• after doping the first semiconductor fin, removing the first mask layer from the second semiconductor fin;
• after removing the first mask layer, forming a second mask layer covering the first semiconductor fin, while leaving the second semiconductor fin exposed;
• with the second mask layer in place, doping a second channel region of the second semiconductor fin with a second dopant to form a second channel doping layer, wherein the second channel region is a channel region of a read-port pull-down transistor of the SRAM cell, wherein after doping the second semiconductor fin with the second dopant, the second channel doping layer in the channel region of the read-port pull-down transistor in the second semiconductor fin has a lower doping concentration than the first channel doping layer in the channel region of the first write-port pull-down transistor in the first semiconductor fin;
• and
• forming a first gate structure across the third semiconductor fin to form a second write-port pull-down transistor, wherein a third channel doping layer in a channel region of the second write-port pull-down transistor in the third semiconductor fin has a lower doping concentration than the first channel doping layer in the channel region of the first write-port pull-down transistor in the first semiconductor fin, but a threshold voltage of the second write-port pull-down transistor is same as a threshold voltage of the first write-port pull-down transistor.