Gray counter and image sensor including the same

A gray counter, comprising:

• a replica circuit configured to generate a first gray code signal from a first clock signal, which is obtained by dividing a clock signal by 2;
• a first flip-flop configured to delay a second clock signal, which is obtained by delaying the first clock signal as much as half a period of the clock signal, and to generate a second gray code signal;
• a second flip-flop configured to receive a first data signal which is a two-divided signal of the second clock signal, to delay the first data signal as much as one period of the second clock signal, and to generate a third gray code signal;
• and
• a third flip-flop configured to divide the third gray code signal by 2, and to generate a fourth gray code signal,
• wherein the gray counter generates the first to fourth gray code signals without a logic circuit or a logic gate not included in the first to third flip-flops.

An image sensor, comprising:

• a pixel sensor configured to sense an incident light, and to output an analog sampling signal;
• a sampler configured to compare the sampling signal and a ramp signal, and to output a comparison signal of time-axis length information;
• and
• a gray counter configured to count a length of the comparison signal in synchronization with a clock signal, and to generate a gray code, the gray counter including:
• a first flip-flop configured to receive a clock signal having a first frequency, and to generate a first gray code signal having a second frequency corresponding to half the first frequency;
• a second flip-flop configured to receive a first data signal which is a four-divided signal of the clock signal, and to generate a second gray code signal having a third frequency corresponding to half the second frequency in response to the clock signal;
• and
• a third flip-flop configured to receive a second data signal which is an eight-divided signal of the clock signal, and to generate a third gray code signal having a fourth frequency corresponding to half the third frequency in response to the clock signal,
• wherein the gray counter generates the first to third gray code signals using only a plurality of flip-flops including the first to third flip-flops.