On-chip multiplexing pixel control circuit

An on-chip multiplexing pixel control circuit for controlling a splicing super-large area array CMOS image sensor, comprising at least one multiplexing unit, each multiplexing unit comprises L levels of serial pixel control sub-circuits and a windowing address gating circuit;

• wherein,
• each level of serial pixel control sub-circuit comprises a row decoding buffer circuit, a row decoding circuit and a combinational logic circuit;
• each windowing address gating circuit comprises a group address buffer circuit, an adder, a group decoding address buffer circuit, and a group decoding circuit;
• the group address buffer circuit is configured to output a group address reference signal to the adder;
• the group decoding circuit is configured to receive an output signal of the adder and a group decoding address of the group decoding address buffer circuit, and perform comparison and selection to output a group decoding signal;
• a receiving terminal of the row decoding circuit is connected to an output terminal of the row decoding buffer circuit;
• the combinational logic circuit is respectively connected to an output terminal of the row decoding circuit and an output terminal of the group decoding circuit through an AND gate circuit, and configured to output a reset signal, a transmission signal and a row gating control signal of a pixel.