Decision feedback equalizer and a device including the same

A device, comprising:

• a reception pad configured to receive a data signal comprising first data and second data, which are sequentially transferred via a channel;
• and
• a decision feedback equalizer configured to equalize the received data signal,
• wherein the decision feedback equalizer comprises:
• a first input latch coupled to the reception pad and configured to generate a first output signal from the first data;
• and
• a second input latch coupled to the reception pad and configured to generate a second output signal from the second data,
• and wherein the second input latch comprises:
• a first sub-circuit configured to generate internal signals having different transition timings according to a result of a comparison between the second data and a reference voltage;
• and
• a second sub-circuit configured to receive the first output signal as feedback and generate the second output signal by compensating for a difference between the transition timings of the internal signals based on the feedback,
• wherein the first and second output signals are return-to-zero signals, and
• the device further comprises:
• a middle latch circuit configured to receive the first and second output signals and convert the first and second output signals into non-return-to-zero signals;
• and
• an output latch circuit configured to output the converted first and second output signals in synchronization with a clock signal,
• wherein the second sub-circuit is further configured to;
• receive a coefficient signal;
• and compensate for a difference between the transition timings of the internal signals, based on the coefficient signal.

A decision feedback equalizer, comprising:

• an input latch circuit configured to output first and second output signals, which are return-to-zero signals, by respectively comparing odd data and even data with a reference voltage;
• a middle latch circuit configured to receive the first and second output signals, convert the first and second output signals into non-return-to-zero signals, and output the converted first and second output signals;
• and
• an output latch circuit configured to receive the converted first and second output signals and output the converted first and second output signals in synchronization with a clock signal,
• wherein the input latch circuit comprises:
• a first input latch comprising a first sub-circuit and a second sub-circuit, the first sub-circuit configured to generate first internal signals by comparing the odd data with the reference voltage, and the second sub-circuit configured to generate the first output signal based on the first internal signals and the second output signal;
• and
• a second input latch comprising a third sub-circuit and a fourth sub-circuit, the third sub-circuit configured to generate second internal signals by comparing the even data with the reference voltage, and the fourth sub-circuit configured to generate the second output signal based on the second internal signals and the first output signal.