Asynchronous chip-to-chip communication
AssigneeSynopsys, Inc.
InventorPramod Bettagere Krishnamurthy
Life of this patent
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Abstract
Systems and methods for asynchronous communication are disclosed. For example, a method for asynchronous communication includes encoding, by a transmitter circuit and according to a first clock signal, a bit sequence by converting a one-bit in the bit sequence into a first sequence and a zero-bit in the bit sequence into a second sequence. A length of the first sequence and a length of the second sequence differ by at least three bits. The method also includes communicating, by the transmitter circuit, the first sequence and the second sequence to a receiver circuit that decodes the first sequence and the second sequence according to a second clock signal that is independent of the first clock signal.
Claims20
A method for asynchronous communication, the method comprising:
- encoding, by a transmitter circuit and according to a first clock signal, a bit sequence by converting a one-bit in the bit sequence into a first sequence and a zero-bit in the bit sequence into a second sequence, wherein a length of the first sequence and a length of the second sequence differ by at least three bits;
- and
- communicating, by the transmitter circuit, the first sequence and the second sequence to a receiver circuit configured to decode the first sequence and the second sequence according to a second clock signal that is independent of the first clock signal.
A system for asynchronous communication, the system comprising:
- a transmitter circuit configured to encode, according to a first clock signal, a bit sequence by converting a one-bit in the bit sequence into a first sequence and a zero-bit in the bit sequence into a second sequence, wherein a length of the first sequence and a length of the second sequence differ based on a difference between a frequency of the first clock signal and a frequency of the second clock signal;
- and
- a receiver circuit configured to receive, from the transmitter circuit, the first sequence and the second sequence and to decode the first sequence and the second sequence according to a second clock signal that is independent of the first clock signal.
A non-transitory computer readable media storing instructions for asynchronous communication that, when executed by a processor, cause the processor to:
- implement a transmitter circuit that encodes, according to a first clock signal, a bit sequence by converting a one-bit in the bit sequence into a first sequence and a zero-bit in the bit sequence into a second sequence, wherein a length of the first sequence and a length of the second sequence differ by at least three bits;
- and
- implement a receiver circuit that receives the first sequence and the second sequence from the transmitter circuit and that decodes the first sequence and the second sequence according to a second clock signal that is independent of the first clock signal.
Dependencies are inferred from the claim text.