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US 11,641,267 B2Granted
Clock and data recovery circuit and source driver including the same
AssigneeSilicon Works Co., Ltd.
InventorsJong Suk Lee, Young Bok Kim, Chung Hwan Son, Seok Jae Oh, Soo Yeun Lee, Yeh Ju Ka
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Abstract
The present disclosure discloses a clock and data recovery circuit. The clock and data recovery circuit may include a clock recovery unit configured to output a recovery clock signal by operating a first time-to-digital conversion circuit or a second time-to-digital conversion circuit depending on a phase difference between a clock of an input signal and the recovery clock signal, and a data recovery unit configured to sample data from the input signal and output recovery data.
Claims20
A clock and data recovery circuit comprising:
- a clock recovery circuit configured to perform first time-to-digital conversion or second time-to-digital conversion on a first phase difference between a clock of an input signal and a recovery clock signal depending on whether the first phase difference is greater than a preset reference phase difference and to output the recovery clock signal, a first clock signal and a second clock signal, wherein phases of the first clock signal and the second clock signal are controlled in response to the first time-to-digital conversion or the second time-to-digital conversion, and a second phase difference between the first clock signal and the recovery clock signal is different from a third phase difference between the second clock signal and the recovery clock signal;
- and
- a data recovery circuit configured to sample data from the input signal by using the first clock signal and the second clock signal and to output recovery data.
A source driver comprising:
- a clock and data recovery circuit configured to generate a recovery clock signal and recovery data from an input signal having a clock training pattern or having data in which a clock has been embedded;
- and
- a data driving circuit configured to generate a data voltage by using the recovery clock signal and the recovery data and to provide the data voltage to a display panel,
- wherein the clock and data recovery circuit comprises:
- a first time-to-digital conversion circuit configured to receive the input signal having the clock training pattern and output a first digital signal corresponding to a first phase difference between a clock of the input signal and the recovery clock signal;
- a second time-to-digital conversion circuit configured to receive the input signal having the data in which the clock has been embedded and output a second digital signal corresponding to the first phase difference;
- a digital loop filter configured to output a control signal corresponding to the first digital signal or the second digital signal;
- and
- a digitally controlled oscillator configured to output the recovery clock signal, a first clock signal and a second clock signal, wherein phases of the first clock signal and the second clock signal are controlled in response to the control signal, and a second phase difference between the first clock signal and the recovery clock signal is different from a third phase difference between the second clock signal and the recovery clock signal.
6 more elements
Dependencies are inferred from the claim text.