Matrix processor generating SAR-searched input delay adjustments to calibrate timing skews in a multi-channel interleaved analog-to-digital converter (ADC)

A calibration matrix method for reducing timing skews among channels in an interleaved Analog-to-Digital Converter (ADC) comprising:

• clearing all bits in all Successive-Approximation-Registers (SARs) that set variable input delays from an analog input to ADCs that are interleaved together, each ADC sampling the analog input and generating an ADC digital output;
• setting bits in a SAR for a reference channel to a midpoint value;
• wherein each channel has a SAR, an ADC, and an input delay element having a variable input delay set by the SAR;
• (a) for each channel:
• inputting the ADC digital outputs from a current channel and from a prior adjacent channel and from a next adjacent channel to a product derivative correlator that generates a sampled product derivative factor that quantifies correlation of the ADC digital output of the current channel to the ADC digital output of prior adjacent cannel and the ADC digital output of the next adjacent channel;
• averaging the sampled product derivative factor over multiple samples of the analog input to generate a product derivative factor for the current channel;
• arranging the product derivative factors for all channels into a factor matrix;
• multiplying the factor matrix by a correlation matrix to generate a sign vector having sign bits corresponding to channels;
• setting a current bit-position to a level-1 Most-Significant Bit (MSB) position in the SARs;
• for all channels except the reference channel:
• (b) setting a test bit at the current bit-position in the SAR of a selected channel to adjust the variable input delay when a sign bit in the sign vector corresponding to the selected channel is 1;
• (c) clearing a test bit at the current bit-position in the SAR of a selected channel to adjust the variable input delay when the sign bit in the sign vector corresponding to the selected channel is 0;
• decreasing the current bit-position and repeating from (a) until the current bit-position is a Least-Significant Bit (LSB) in the SARs;
• ending calibration when all product derivative correlators have been used to adjust settings in the SARs to adjust the variable input delays to minimize timing skews among all channels.

A calibrating-matrix interleaved Analog-to-Digital Converter (ADC) comprising:

• a plurality of N channels, wherein N is a whole number of at least 3, each channel comprising:
• an ADC having a sampled analog input and a digital output;
• a sampling switch between an analog input and the sampled analog input, the sampling switch responsive to a delayed clock;
• a Successive-Approximation-Register (SAR) that stores a delay setting;
• a delay element generating a variable delay between an input clock and the delayed clock, wherein the variable delay is determined by the delay setting in the SAR;
• a filter for generating a filtered channel output from the digital output of the ADC;
• a product derivative correlator, receiving the filtered channel output of a channel and the filtered channel outputs from adjacent channels, the product derivative correlator generating a product derivative factor indicating a correlation of the channel to the adjacent channels;
• a matrix processor that receives a plurality of the product derivative factor from the product derivative correlator for the plurality of N channels and generates a sign-bit vector by multiplying the plurality of the product derivative factor with a correlation matrix;
• and
• a calibrator, using each sign bit in the sign-bit vector to decide when to add a test bit to the SAR for a channel, and when to remove the test bit from the SAR for the channel, wherein each sign bit in the sign-bit vector is for adding or removing a test bit from a SAR in a different channel in the plurality of N channels.