Slew rate adjusting circuit for adjusting slew rate, buffer circuit including same, and slew rate adjusting method
AssigneeMagnaChip Semiconductor, Ltd.
InventorsJung Hoon Sul, Dong Il Seo
Life of this patent
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Abstract
A slew rate adjusting circuit includes an adjustment transistor configured to provide an adjustment current into an output port of an arithmetic amplifier, a first transistor connected between a power line of the arithmetic amplifier and the adjustment transistor, and a second transistor connected between the first transistor and an output node of the output port, wherein the adjustment transistor is turned on by the second transistor in response to a difference between an input voltage and an output voltage being equal to or greater than a reference voltage, and the adjustment current is provided to the output port in response to the adjustment transistor being turned on.
Claims14
A buffer circuit, comprising:
- an arithmetic amplifier configured to output an output voltage through an output node by amplifying an input voltage;
- an adjustment current generating circuit comprising an adjustment transistor and configured to provide an adjustment current to an output port of the arithmetic amplifier so as to adjust a slew rate of the output port;
- a compensation capacitor connected between the arithmetic amplifier and a drain terminal of the adjustment transistor, and configured to perform a compensation operation, the drain terminal of the adjustment transistor being directly connected to both the output node and the compensation capacitor;
- and
- a control circuit connected to a gate terminal of the adjustment transistor to control the adjustment current generating circuit so as to provide the adjustment current to the output node in response to a difference between the input voltage and the output voltage being equal to or greater than a reference voltage.
A slew rate adjusting method, the method comprising:
- receiving an input voltage input to an arithmetic amplifier;
- receiving an output voltage output from the arithmetic amplifier;
- performing a compensation operation using a compensation capacitor connected between the arithmetic amplifier and a drain terminal of an adjustment transistor, the drain terminal of the adjustment transistor being directly connected to both the output node and the compensation capacitor;
- and
- providing an adjustment current, by using a control circuit configured to control the adjustment transistor, to an output node of an output port of the arithmetic amplifier on the basis of a difference between the input voltage and the output voltage so as to decrease a transition time of the output voltage,
- wherein a gate terminal of the adjustment transistor is connected to the control circuit, and the drain terminal of the adjustment transistor is connected to the output node.
A buffer circuit, comprising:
- an arithmetic amplifier configured to output an output voltage through an output node by amplifying an input voltage;
- an adjustment current generating circuit comprising an adjustment transistor and configured to provide an adjustment current to an output port of the arithmetic amplifier so as to adjust a slew rate of the output port;
- a control circuit connected to a gate terminal of the adjustment transistor to control the adjustment current generating circuit so as to provide the adjustment current to the output node in response to a difference between the input voltage and the output voltage being equal to or greater than a reference voltage, and comprising a first transistor connected to a power line and a second transistor connected between the first transistor and the output node;
- and
- an enable transistor connected in series between the first transistor and the second transistor,
- wherein the enable transistor is further connected to the adjustment transistor connected between the power line, the output node, and the control circuit, and
- wherein the enable transistor is configured to control whether to turn on the second transistor in response to an enable signal.
Dependencies are inferred from the claim text.