High-speed switch with accelerated switching time
AssigneepSemi Corporation
InventorChengkai Luo
Life of this patent
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Abstract
A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch.
Claims15
A switch branch comprising:
- (a) a field effect transistor (FET) coupled between a switch branch input and a switch branch output, the FET having a gate controlled by a gate signal;
- (b) a switch control input configured to receive control signals to be applied to the gate of the FET;
- (c) a reset circuit coupled between the switch control input and the gate of the FET, the reset circuit having a reference potential input and a reset control port;
- wherein the reset circuit couples the gate of the FET to the reference potential input during a reset period defined by a reset pulse received through the reset control port, the reset pulse being generated in response to a change in state of the control signals applied to the switch control input;
- and
- wherein the reset circuit couples the gate of the FET to the switch control input in the absence of the reset pulse.
A switch branch comprising:
- (a) a switch input;
- (b) a switch output;
- (c) at least one field effect transistor (FET) series-coupled between the switch input and the switch output, each FET having a gate controlled by a common gate signal;
- (d) a switch control input configured to receive control signals to be applied to the gate of the FET;
- (e) a reset circuit including:
- (1) a signal input coupled to the switch control input;
- (2) a signal output coupled to the gate of the at least one FET;
- (3) a reference potential input;
- (4) a reset control port;
- (5) a series switch coupled between the signal input and the signal output;
- and
- (6) a shunt switch coupled between the signal output and the reference potential input;
- wherein the reset circuit closes the shunt switch and opens the series switch during a reset period defined by a reset pulse received through the reset control port, the reset pulse being generated in response to a change in state of the control signals applied to the switch control input;
- and
- wherein the reset circuit opens the shunt switch and closes the series switch in the absence of the reset pulse.
Dependencies are inferred from the claim text.