Semiconductor device and manufacturing method thereof

A semiconductor device comprising a transistor comprising:

• an oxide semiconductor layer;
• a gate insulating layer over the oxide semiconductor layer;
• a gate electrode overlapping with the oxide semiconductor layer with the gate insulating layer provided therebetween, the gate electrode comprising a first layer and a second layer provided over the first layer;
• a first conductive layer over the oxide semiconductor layer, the first conductive layer configured to be one of a source electrode and a drain electrode of the transistor;
• and
• a first insulating layer over the gate electrode, the first insulating layer having a region being in contact with a top surface of the gate insulating layer,
• wherein in a cross-sectional view parallel to a channel length direction of the transistor, an end portion of the first layer of the gate electrode is positioned on an outer side than an end portion of the second layer of the gate electrode,
• wherein in the cross-sectional view parallel to the channel length direction of the transistor, an end portion of the gate insulating layer is positioned on an outer side than the end portion of the first layer of the gate electrode,
• wherein in the cross-sectional view parallel to the channel length direction of the transistor, the oxide semiconductor layer comprises a channel formation region, a first region being adjacent to the channel formation region and being in contact with the gate insulating layer, a second region being in contact with the first conductive layer, and a third region being adjacent to the first region and being in contact with the first insulating layer, and
• wherein a thickness of the second region is smaller than a thickness of the first region.

A semiconductor device comprising a transistor comprising:

• an oxide semiconductor layer;
• a gate insulating layer over the oxide semiconductor layer;
• a gate electrode overlapping with the oxide semiconductor layer with the gate insulating layer provided therebetween, the gate electrode comprising a first layer and a second layer provided over the first layer;
• a first conductive layer over the oxide semiconductor layer, the first conductive layer configured to be one of a source electrode and a drain electrode of the transistor;
• and
• a first insulating layer over the gate electrode, the first insulating layer having a region being in contact with a top surface of the gate insulating layer and a side surface of the first layer of the gate electrode,
• wherein in a cross-sectional view parallel to a channel length direction of the transistor, an end portion of the first layer of the gate electrode is positioned on an outer side than an end portion of the second layer of the gate electrode,
• wherein in the cross-sectional view parallel to the channel length direction of the transistor, an angle between a side surface of the first layer of the gate electrode and the top surface of the gate insulating layer is less than an angle between a side surface of the second layer of the gate electrode and a top surface of the first layer of the gate electrode, and
• wherein in the cross-sectional view parallel to the channel length direction of the transistor, the oxide semiconductor layer comprises a channel formation region, a first region being adjacent to the channel formation region and being in contact with the gate insulating layer, a second region being in contact with the first conductive layer, and a third region located between the first region and the second region and being in contact with the first insulating layer.