Ferroelectric field effect transistors (FeFETs) having band-engineered interface layer

An integrated circuit structure, comprising:

• a semiconductor fin above a substrate, the semiconductor fin having a top and sidewalls;
• an insulating layer intervening between the semiconductor fin and the substrate, wherein the semiconductor fin is directly on the insulating layer;
• a metal oxide material on the top and sidewalls of the semiconductor fin, the metal oxide material having no net dipole, and the metal oxide material having an uppermost surface;
• a ferroelectric oxide material on the metal oxide material on the top and sidewalls of the semiconductor fin, the ferroelectric oxide material having an uppermost surface co-planar with the uppermost surface of the metal oxide material;
• a gate electrode on the ferroelectric oxide material above the top and laterally adjacent to the sidewalls of the semiconductor fin, the gate electrode having a first side and a second side opposite the first side, wherein a portion of the ferroelectric oxide material is on the first side and the second side of the gate electrode, wherein a portion of the metal oxide material is on the portion of the ferroelectric oxide material on the first side and the second side of the gate electrode, and wherein the gate electrode has an uppermost surface co-planar with the uppermost surface of the ferroelectric oxide material;
• a first source/drain region at the first side of the gate electrode;
• and
• a second source/drain region at the second side of the gate electrode.

An integrated circuit structure, comprising:

• a semiconductor nanowire above a substrate, the semiconductor nanowire having a top, a bottom and sidewalls;
• a metal oxide material on the top, bottom and sidewalls of the semiconductor nanowire, the metal oxide material having no net dipole, and the metal oxide material having an uppermost surface;
• a ferroelectric oxide material on the metal oxide material on the top, bottom and sidewalls of the semiconductor nanowire, the ferroelectric oxide material having an uppermost surface co-planar with the uppermost surface of the metal oxide material;
• a gate electrode on the ferroelectric oxide material above the top, below the bottom and laterally adjacent to the sidewalls of the semiconductor nanowire, the gate electrode having a first side and a second side opposite the first side, wherein a portion of the ferroelectric oxide material is on the first side and the second side of the gate electrode, wherein a portion of the metal oxide material is on the portion of the ferroelectric oxide material on the first side and the second side of the gate electrode, and wherein the gate electrode has an uppermost surface co-planar with the uppermost surface of the ferroelectric oxide material;
• a first source/drain region at the first side of the gate electrode;
• and
• a second source/drain region at the second side of the gate electrode.