Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

An integrated circuit structure, comprising:

• a first pair of semiconductor fin structures, comprising:
• a first semiconductor fin structure;
• and
• a second semiconductor fin structure, the first and second semiconductor fin structures being spaced at first fin pitch;
• a second pair of semiconductor fin structures, comprising:
• a third semiconductor fin structure;
• and
• a fourth semiconductor fin structure, the third and fourth semiconductor fin structures being spaced at a second fin pitch, the second fin pitch substantially the same as the first fin pitch;
• a first source or drain region on the first semiconductor fin structure;
• a second source or drain region on the second semiconductor fin structure, wherein the second source or drain region is not merged nor in contact with the first source or drain region;
• a third source or drain region on the third semiconductor fin structure;
• and
• a fourth source or drain region on the fourth semiconductor fin structure, wherein the fourth source or drain region is merged with the third source or drain region.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first pair of semiconductor fins, comprising:
• a first semiconductor fin;
• and
• a second semiconductor fin, the second semiconductor fin spaced apart from the first semiconductor fin by a first fin-to-fin distance;
• a second pair of semiconductor fins, comprising:
• a third semiconductor fin;
• and
• a fourth semiconductor fin, the fourth semiconductor fin spaced apart from the third semiconductor fin by a second fin-to-fin distance, the second fin-to-fin distance substantially the same as the first fin-to-fin distance;
• a first epitaxial source or drain region on the first semiconductor fin;
• a second epitaxial source or drain region on the second semiconductor fin, wherein the second epitaxial source or drain region is not merged nor in contact with the first epitaxial source or drain region;
• a third epitaxial source or drain region on the third semiconductor fin;
• and
• a fourth epitaxial source or drain region on the fourth semiconductor fin, wherein the fourth epitaxial source or drain region is merged with the third epitaxial source or drain region.