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US 11,640,983 B2Granted
Semiconductor device and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShahaji B. More, Chandrashekhar Prakash Savant
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Abstract
In an embodiment, a device includes: a gate dielectric over a substrate; a gate electrode over the gate dielectric, the gate electrode including: a work function tuning layer over the gate dielectric; a glue layer over the work function tuning layer; a fill layer over the glue layer; and a void defined by inner surfaces of at least one of the fill layer, the glue layer, and the work function tuning layer, a material of the gate electrode at the inner surfaces including a work function tuning element.
Claims20
A device comprising:
- a gate dielectric over a substrate;
- a gate electrode over the gate dielectric, the gate electrode comprising:
- a work function tuning layer over the gate dielectric;
- a glue layer over the work function tuning layer;
- a fill layer over the glue layer;
- a void defined by inner surfaces of at least one of the fill layer, the glue layer, and the work function tuning layer, a material of the gate electrode at the inner surfaces comprising a work function tuning element;
- and
- an isolation region adjacent an end of the gate electrode, the void further defined by a sidewall of the isolation region.
5 more elements
A device comprising:
- a first transistor comprising:
- a first channel region, the first channel region having a first length;
- and
- a first gate structure over the first channel region, the first gate structure comprising a first gate electrode, the first gate electrode having a void therein;
- and
- a second transistor comprising:
- a second channel region, the second channel region having a second length, the second length greater than the first length;
- and
- a second gate structure over the second channel region, the second gate structure comprising a second gate electrode, the second gate electrode being free of voids, the second gate electrode having a different work function than the first gate electrode.
6 more elements
A method comprising:
- removing a dummy gate to form a recess between gate spacers;
- depositing a gate dielectric layer in the recess;
- depositing gate electrode layers on the gate dielectric layer, inner surfaces of the gate electrode layers defining a void;
- planarizing top surfaces of the gate electrode layers until the void is exposed at the top surfaces of the gate electrode layers;
- and
- performing a first gate treatment process in the void, the first gate treatment process increasing a concentration of a work function tuning element at the inner surfaces of the gate electrode layers that define the void.
3 more elements
Dependencies are inferred from the claim text.