Memory array isolation structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, Tsuching Yang, Yu-Wei Jiang
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Abstract
A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line; and a dielectric material separating the source line and the bit line. The dielectric material forms an interface with the OS layer. The dielectric material comprises hydrogen, and a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).
Claims20
A memory cell, comprising:
- a thin film transistor over a semiconductor substrate, the thin film transistor comprising:
- a memory film contacting a word line;
- and
- an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line;
- and
- a dielectric material separating the source line and the bit line, wherein the dielectric material forms an interface with the OS layer, wherein the dielectric material comprises hydrogen, and wherein a hydrogen concentration at the interface between the dielectric material and the OS layer is no more than 3 atomic percent (at %).
A device, comprising:
- a semiconductor substrate;
- a first memory cell over the semiconductor substrate, the first memory cell comprising a first thin film transistor, wherein the first thin film transistor comprises:
- a gate electrode comprising a portion of a first word line;
- a first portion of a ferroelectric material, the first portion of the ferroelectric material being on a sidewall of the first word line;
- and
- a first channel region on a sidewall of the ferroelectric material, the first channel region comprising hydrogen, and a hydrogen concentration of the first channel region being in a range of 1020 atoms per cubic centimeter to 1022 atoms per cubic centimeter;
- a source line, wherein a first portion of the source line provides a first source/drain electrode for the first thin film transistor;
- a bit line, wherein a first portion of the bit line provides a second source/drain electrode for the first thin film transistor;
- a first dielectric material separating the source line and the bit line, wherein the first dielectric material physically contacts the first channel region;
- and
- a second memory cell over the first memory cell.
A memory device, comprising:
- a thin film transistor over a semiconductor substrate, the thin film transistor comprising:
- a ferroelectric material contacting a word line;
- and
- an oxide semiconductor (OS) layer, wherein the ferroelectric material is disposed between the OS layer and the word line;
- a source line and a bit line each extending along a direction that is perpendicular to a direction in which the word line extends and is further perpendicular to a major surface of the semiconductor substrate;
- a first dielectric material between the source line and the bit line, wherein the first dielectric material touches the OS layer;
- and
- a second dielectric material between the source line and the bit line, wherein the second dielectric material is separated from the OS layer by the first dielectric material, and wherein the first dielectric material has a hydrogen concentration lower than a hydrogen concentration of the second dielectric material.
Dependencies are inferred from the claim text.