Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device, comprising:

• providing a substrate including a first region and a second region,
• forming a first fin-type structure on the first region and a second fin-type structure on the second region, wherein the first fin-type structure and the second fin-type structure respectively include a first semiconductor pattern and a second semiconductor pattern alternatively stacked on the substrate,
• performing an ion implantation on the second region except on the first region, wherein an impurity concentration of the second semiconductor pattern on the second region is higher than the impurity concentration of the second semiconductor pattern on the first region,
• forming a first dummy gate electrode intersecting the first fin-type pattern and a second dummy gate electrode intersecting the second fin-type pattern,
• forming a first spacer on a side wall of the first dummy gate electrode and a second spacer on a side wall of the second dummy gate electrode,
• forming a first source/drain on a side of the first dummy gate electrode and a second source/drain on a side of the second dummy gate electrode,
• removing the first dummy gate electrode and the second dummy gate electrode, and
• removing completely the first semiconductor pattern on the first region and a portion of the first semiconductor pattern on the second region, wherein the first semiconductor pattern on the second region remains to form a supporting pattern.

A method for fabricating a semiconductor device, comprising:

• providing a substrate including a first region and a second region,
• forming a first fin-type structure on the first region and a second fin-type structure on the second region, wherein the first fin-type structure and the second fin-type structure respectively include a first semiconductor pattern and a second semiconductor pattern alternately stacked on the substrate,
• forming a blocking film covering the first region and exposing the second region,
• performing an ion implantation on the second region to lower an etch selectivity of the first semiconductor pattern on the second region,
• removing the blocking film,
• forming a first dummy gate electrode intersecting the first fin-type pattern and a second dummy gate electrode intersecting the second fin-type pattern,
• forming a first spacer on a side wall of the first dummy gate electrode and a second spacer on a side wall of the second dummy gate electrode,
• forming a first source/drain on a side of the first dummy gate electrode and a second source/drain on a side of the second dummy gate electrode,
• removing the first dummy gate electrode and the second dummy gate electrode, and
• etching the first semiconductor pattern, wherein the first semiconductor pattern on the first region is completely removed, and the first semiconductor pattern on the second region remains to form a supporting pattern, and wherein a width of the first semiconductor pattern on the second region is greater than a width of the second semiconductor pattern on the second region,
• forming a first gate insulating layer on the second semiconductor pattern on the first region and a second gate insulating layer on the first semiconductor pattern and the second semiconductor pattern on the second region, and
• forming a first gate electrode on the first gate insulating layer and a second gate electrode on the second gate insulating layer.