Process for fabricating a high-voltage capacitive element, and corresponding integrated circuit
AssigneeSTMicroelectronics (Rousset) SAS
InventorAbderrezak Marzaki
Life of this patent
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Abstract
A semiconductor substrate has a front face with a first dielectric region. A capacitive element includes, on a surface of the first dielectric region at the front face, a stack of layers which include a first conductive region, a second conductive region and a third conductive region. The second conductive region is electrically insulated from the first conductive region by a second dielectric region. The second conductive region is further electrically insulated from the third conductive region by a third dielectric region. The first and third conductive regions form one plate of the capacitive element, and the second conductive region forms another plate of the capacitive element.
Claims9
A method for fabricating an integrated circuit on a semiconductor substrate having a front face, comprising:
- forming a trench isolation structure in the semiconductor substrate at said front face;
- forming a trench extending into the front face of the semiconductor substrate;
- depositing a first conductive layer that forms a first conductive electrode for a capacitor on the trench isolation structure and forms a gate electrode for a vertical gate transistor in said trench;
- depositing a first dielectric layer that forms a first capacitor dielectric layer for said capacitor on the first conductive electrode and forms a tunnel dielectric layer for a floating gate transistor on the semiconductor substrate;
- depositing a second conductive layer that forms a second conductive electrode for said capacitor on the first capacitor dielectric layer and forms a floating gate electrode for said floating gate transistor on the tunnel dielectric layer;
- depositing a second dielectric layer that forms a second capacitor dielectric layer for said capacitor on the second conductive electrode and forms a gate dielectric layer for said floating gate transistor on the floating gate electrode;
- and
- depositing a third conductive layer that forms a third conductive electrode for said capacitor on the second capacitor dielectric layer and forms a control gate electrode for said floating gate transistor on the gate dielectric layer.
A method for fabricating an integrated circuit on a semiconductor substrate having a front face, comprising:
- forming a trench isolation structure in the semiconductor substrate at said front face;
- forming a trench extending into the front face of the semiconductor substrate;
- depositing a first conductive layer that forms a first conductive electrode for a capacitor on the trench isolation structure and forms a gate electrode for a vertical gate transistor in said trench;
- depositing a first dielectric layer that forms a first capacitor dielectric layer for said capacitor on the first conductive electrode and forms a gate dielectric layer for a field effect transistor on the semiconductor substrate;
- depositing a second conductive layer that forms a second conductive electrode for said capacitor on the first capacitor dielectric layer and forms a gate electrode for said field effect transistor on the tunnel dielectric layer;
- depositing a second dielectric layer that forms a second capacitor dielectric layer for said capacitor on the second conductive electrode;
- and
- depositing a third conductive layer that forms a third conductive electrode for said capacitor on the second capacitor dielectric layer.
Dependencies are inferred from the claim text.