SMID processing unit performing concurrent load/store and ALU operations
AssigneeVsora
InventorsKhaled Maalej, Trung-Dung Nguyen, Julien Schmitt, Pierre-Emmanuel Bernard
Life of this patent
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Abstract
A computing device comprising: a plurality of ALUs; a set of registers; a memory; a memory interface between the registers and the memory; a control unit controlling the ALUs by generating: at least one cycle i including both implementing at least one first computing operation by way of an arithmetic logic unit and downloading a first dataset from the memory to at least one register; at least one cycle ii, following the at least one cycle i, including implementing a second computing operation by way of an arithmetic logic unit, for which second computing operation at least part of the first dataset forms at least one operand.
Claims10
A computing device comprising:
- a plurality of arithmetic logic units;
- a set of registers able to supply data of operand type to the inputs of said arithmetic logic units and able to be supplied with data from the outputs of said arithmetic logic units;
- a memory;
- a memory interface by way of which data are transmitted and routed between the registers and the memory;
- a control unit configured so as to control the arithmetic logic units in accordance with a processing chain microarchitecture such that the arithmetic logic units perform computing operations in parallel with one another, the control unit furthermore being designed to control the memory access operations by way of the memory interface,
- said control operations generating:
- at least one cycle i including both implementing at least one first computing operation by way of an arithmetic logic unit and downloading a first dataset from the memory to at least one register;
- at least one cycle ii, following the at least one cycle i, including implementing a second computing operation by way of an arithmetic logic unit, for which second computing operation at least part of the first dataset forms at least one operand,
- content of said first dataset to download being selected to comprise at least one operand of said second computing operation, and the number of data of the downloaded first dataset being selected to comprise the maximum of the data that can be read during a single cycle such that it further comprises data which are not identified as operands of next computing operations.
A data processing method implemented by a control unit of a computing device, said device comprising:
- a plurality of arithmetic logic units;
- a set of registers able to supply data of operand type to the inputs of said arithmetic logic units and able to be supplied with data from the outputs of said arithmetic logic units;
- a memory;
- a memory interface by way of which data are transmitted and routed between the registers and the memory;
- the control unit configured so as to control the arithmetic logic units in accordance with a processing chain microarchitecture such that the arithmetic logic units perform computing operations in parallel with one another, the control unit furthermore being designed to control the memory access operations by way of the memory interface;
- said method comprising at least:
- generating a cycle i including both implementing at least one first computing operation by way of an arithmetic logic unit and downloading a first dataset from the memory to at least one register;
- generating a cycle ii, following the cycle i, including implementing a second computing operation by way of an arithmetic logic unit, for which second computing operation at least part of the first dataset forms at least one operand,
- the content of said first dataset to download being selected to comprise at least one operand of said second computing operation, and the number of data of the downloaded first dataset being selected to comprise the maximum of the data that can be read during a single cycle such that it further comprises data which are not identified as operands of next computing operations.
Dependencies are inferred from the claim text.