Phase synchronized LO generation

A method for controlling an internal reset signal that is synchronous to a clock signal, the method comprising:

• receiving the clock signal through a clock switch circuit;
• enabling the internal reset signal through a plurality of serially coupled D flip-flops (DFFs) in response to an external reset signal being enabled;
• and
• disabling the internal reset signal through the plurality of serially coupled DFFs after a predefined number of clock signal cycles after the external reset signal is disabled, wherein
• the clock switch circuit outputs the clock signal in an on state and blocks the clock signal in an off state, and
• the plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal output from the clock switch circuit, wherein
• each of the plurality of serially coupled DFFs includes a data input terminal, a data output terminal, a clock input terminal, and a reset terminal, and the data output terminal of one of two adjacent coupled DFFs is coupled to the data input terminal of the other one of the two adjacent coupled DEB.

An electronic system comprising a local divider reset (LORST) circuitry configured to:

• receive a clock signal through a clock switch circuit;
• enable an internal reset signal through a plurality of serially coupled D flip-flops (DFFs) in response to an external reset signal being enabled;
• and
• disable the internal reset signal through the plurality of serially coupled DFFs after a predefined number of clock signal cycles after the external reset signal is disabled, wherein
• the clock switch circuit outputs the clock signal in an on state and blocks the clock signal in an off state, and
• the plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal output from the clock switch circuit, wherein
• each of the plurality of serially coupled DFFs includes a data input terminal, a data output terminal, a clock input terminal, and a reset terminal, and the data output terminal of one of two adjacent coupled DFFs is coupled to the data input terminal of the other one of the two adjacent coupled DFFs.