Method for processing a semiconductor device with two closely spaced gates
AssigneeImec Vzw
InventorsBoon Teik Chan, Ruoyu Li, Stefan Kubicek, Julien Jussot
Life of this patent
Estimating the term…
Abstract
A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.
Claims16
A method for processing a semiconductor device comprising two gates separated by a lateral spacing, the method comprising:
- forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the lateral spacing;
- forming a gate layer on and around the template structure;
- removing a part of the gate layer formed on the template structure;
- forming an etch mask on a portion of a remaining gate layer;
- etching based on the etch mask the remaining gate layer to form a gate structure including the two gates, wherein the etch mask is aligned to the template structure;
- and
- selectively removing the template structure, wherein the lateral spacing between the two gates is formed by removal of the at least one sub-structure of the template structure;
- and wherein the lateral spacing is 50 nm or less.
Dependencies are inferred from the claim text.