Self-aligned select gate cut for 3D NAND

A method of forming a memory device, the method comprising:

• opening a plurality of memory holes in a stack of alternating silicon layers and nitride layers, the silicon layers and nitride layers lying along a plane formed by a first direction and a second direction with a thickness extending along a third direction, and the openings extending along the third direction;
• filling the memory holes with a core oxide, a memory hole semiconductor material and a memory hole nitride layer;
• forming a cut line along the first direction between adjacent memory hole rows the cut line positioned to cover a portion of the memory holes from a first memory hole line and a portion of memory holes from an adjacent second memory hole line;
• and
• filling the cut line with a dielectric.

A method of forming a memory device, the method comprising:

• opening a plurality of memory holes through a first layer stack on a second layer stack, the first layer stack comprising alternating silicon layers and nitride layers, the second layer stack comprising alternating oxide layers and nitride layers, each of the layers of the first layer stack and the second layer stack lying along a plane formed by a first direction and a second direction and having a thickness along a third direction, and the openings extend along the third direction, the plurality of memory holes are staggered to provide a plurality of memory hole lines having spaced memory holes along the first direction so that adjacent memory hole lines have the memory holes in a staggered configuration;
• forming a conformal oxide layer on the first layer stack and sidewalls of the memory holes;
• forming a conformal memory hole nitride layer on the conformal oxide layer;
• forming a conformal semiconductor material layer on the conformal memory hole nitride layer;
• filling the memory hole with a core oxide;
• removing overburden material to expose a top surface of the core oxide and a top surface of the semiconductor material and the conformal memory hole nitride layer;
• forming a slit extending along the first direction through at least the first layer stack, the slit having a width along the second direction and a depth along the third direction;
• recessing the nitride layers of the first layer stack through the slit to leave memory layer gaps and expose first and second surfaces of the silicon layers;
• forming an oxide layer in the memory layer gaps;
• forming a barrier layer on the oxide layer in the memory layer gaps;
• filling the memory layer gaps with a conductive material;
• forming a cut line along the first direction between adjacent memory hole rows the cut line positioned to cover a portion of the memory holes from a first memory hole line and a portion of memory holes from an adjacent second memory hole line;
• and
• filling the cut line with a dielectric.