Coding schemes for communicating multiple logic states through a digital isolator
AssigneeAnalog Devices, Inc.
InventorsEric C. Gaalaas, Dongwan Ha, Jason J. Ziomek, Bikiran Goswami, Brian Jadus
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Abstract
Methods and apparatus are disclosed for communicating multiple logic states across a digital isolator. The digital isolator is a universal serial bus (USB) isolator in some embodiments. The digital isolator includes one or more single-bit data channels. Three or more logic states of information are transmitted across the single-bit data channel(s). The logic states are distinguished by a pulse sequence, and in particular a number of edges of the pulse sequence and a final value or final edge of the pulse sequence.
Claims20
A method for processing a digital pulse sequence transmitted across an isolation barrier of a digital isolator and representing a logic state of a data signal line, the method comprising:
- during a fixed period, counting a number of edges of the digital pulse sequence;
- determining a polarity of a representative edge of the digital pulse sequence or a final value of the digital pulse sequence during the fixed period;
- and
- determining the logic state from:
- (A) the number of edges, and
- (B) the polarity of the representative edge or the final value of the digital pulse sequence.
A receiver for processing a digital pulse sequence received across an isolation barrier of a digital isolator and representing a logic state of a data signal line, comprising:
- an edge detector circuit configured to sample the received digital pulse sequence during a fixed time period, and further configured to produce an output signal responsive to one or more rising or falling edges detected in the received digital pulse sequence during the fixed time period;
- a counter circuit configured to count a total number of edges detected by the edge detector circuit during the fixed time period based on the output signal of the edge detector circuit;
- and
- a decode logic circuit configured to:
- determine a polarity of a representative edge of the digital pulse sequence or a final value of the digital pulse sequence during the fixed period, based on the output of the edge detector circuit, and determine the logic state from:
- (A) the total number of edges counted by the counter circuit during the fixed time period, and
- (B) the polarity of the representative edge or the final value of the digital pulse sequence.
A coding method for communicating at least three logic states across a digital isolator channel having an isolation barrier between different voltage domains, the method comprising:
- receiving at the digital isolator a data signal representing a logic state;
- encoding the logic state as a pulse sequence having (A) a number of edges, and (B) a final value or representative edge, uniquely identifying the logic state;
- and
- transmitting the pulse sequence across the isolation barrier.
Dependencies are inferred from the claim text.