Low-latency forward error correction for high-speed serial links
AssigneeIntel Corporation
InventorDebendra Das Sharma
Life of this patent
Estimating the term…
Abstract
Systems and devices can include a port for transmitting data; and a link coupled to the port. The port, in preparation to transmit a data block across the link, to determine a size of a burst of data to be transmitted across the link; determine a plurality of error correcting code words for forward error correction based on the size of the burst of data; interleave each of the plurality of error correcting code words to correspond with consecutive symbols of the burst of data; and transmit the burst of data comprising the interleaved plurality of error correcting code across the link.
Claims12
An apparatus comprising:
- a port for transmitting data;
- and
- a link coupled to the port to:
- determine a size of a burst of data to be transmitted across the link;
- determine a plurality of error correcting codes for forward error correction of the burst of data based on the size of the burst of data;
- and
- transmit the burst of data and the plurality of error correcting codes across the link, wherein the error correcting code words are interleaved in the transmission such that three consecutive bytes in the transmission include a first byte comprising a portion of a first error correcting code, a second byte comprising a portion of a second error correcting code, and a third byte comprising a portion of a third error correcting code.
A method comprising:
- determining a size of a burst of data to be transmitted across a link;
- determining a plurality of error correcting codes for forward error correction of the burst of data based on the size of the burst of data;
- and
- transmitting the burst of data and the error correcting code across the link, wherein the error correcting code words are interleaved in the transmission such that three consecutive bytes in the transmission include a first byte comprising a portion of a first error correcting code, a second byte comprising a portion of a second error correcting code, and a third byte comprising a portion of a third error correcting code.
Dependencies are inferred from the claim text.