Method for time stamping with increased accuracy
AssigneeXilinx, Inc.
InventorPaolo Novellini
Life of this patent
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Abstract
A method for measuring asynchronous timestamp requests includes receiving a timestamp (“TS”) request from a client device during a first interval of a time of day (“TOD”) clock, and calculating, using the TOD clock, at a next interval of the TOD clock, a TS correction of the TS request relative to a reference point of the first TOD clock interval. The method further includes adding the TS correction to the reference point of the first interval of the TOD clock, and outputting the corrected TS to the client device.
Claims20
A method for timestamping in electronic devices, comprising:
- receiving a timestamp (“TS”) request from a client device during a first interval of a time of day (TOD) clock, the TS request based on a first local clock of the client device, the TOD clock remote from the client;
- calculating, using the TOD clock, at a next interval of the TOD clock, a TS correction of the TS request relative to a reference point of the first interval of the TOD clock;
- adding the TS correction to the reference point of the first interval of the TOD clock to define a position of the TS request inside of a TOD clock interval;
- and
- outputting a corrected TS to the client device.
A circuit for calculating timestamp corrections, comprising:
- a single clock tree fed by a time of day (TOD) clock;
- and
- a set of digital phase locked loops (“DPLLs”), each DPLL including:
- an input interface configured to receive a timestamp (“TS”) request from a client device during a first interval of the TOD clock;
- a phase detector configured to detect a phase of a clock associated with the TS request;
- a numerically controlled oscillator (“NCO”), configured to receive the TS request and its phase and calculate a TS correction for the TS request relative to the TOD clock;
- and
- an output interface, configured to output the TS correction.
A circuit for calculating timestamp corrections, comprising:
- a single clock tree fed by a first clock;
- a set of digital phase locked loops (“DPLLs”), each DPLL including:
- an input interface configured to receive a timestamp (“TS”) request from a client device during a first interval of the first clock;
- a phase detector configured to detect a phase of a requesting device clock associated with the TS request;
- a numerically controlled oscillator (“NCO”) configured to receive the TS request and its phase and calculate a TS correction for the TS request relative to the first clock;
- and
- a subtractor configured to receive the TS correction and a time of day (TOD) clock correction, subtract the TOD clock correction from the TS correction, and output a normalized TS correction relative to a first interval of the TOD clock;
- and
- a TOD clock DPLL, including:
- an input interface configured to receive a TOD clock signal;
- a phase detector configured to detect a phase of the TOD clock;
- a numerically controlled oscillator (“NCO”) configured to receive the TOD clock signal and calculate a TOD clock correction between the TOD clock and the first clock;
- and
- an output, interface configured to output the TOD clock correction to each respective subtractor of the set of DPLLs.
Dependencies are inferred from the claim text.