Decoding circuit and chip

A decoding circuit for decoding, in accordance with decoding rules of a home bus system (HBS) protocol, a signal transmitted using the HBS protocol, the decoding rules of the HBS protocol including decoding the signal “01” as “00” and decoding the signal “11” as “11”, the decoding circuit comprising, connected in a sequence, a charge/discharge unit, a capacitor and a conversion unit, wherein

• the charge/discharge unit configured to charge the capacitor in response to a reception of a first level and to discharge the capacitor in response to a reception of a second level, wherein a ratio of a total time required to transfer any amount of charge into the capacitor to a total time required to transfer the same amount of charge from the capacitor is a predetermined value,
• the conversion unit configured to output a third level when a voltage on the capacitor exceeds a predetermined voltage and to otherwise output a fourth level, wherein the predetermined voltage is equal in magnitude to a voltage on the capacitor resulting from a noise spike in the first level,
• the first level being low, the second level being high, the third level being low, the fourth level being high, and
• the capacitor configured to eliminate any adverse effect of noise in a transmitted signal and to be self-adaptive to signals transmitted at different clock rates.