Back to results
US 11,637,561 B2Granted
Method of data conversion for computing-in-memory
AssigneeIP Great Incorporated
InventorYuan-Ju Chao
Life of this patent
Estimating the term…
Abstract
Computing-in-memory utilizes memory as weight for multiply-and-accumulate (MAC) operations. Input data multiplies weights to produce output data during the operation. Method of data conversion from input data, memory element to output data is described to enhance the computing efficiency.
Claims18
A data converter for computing-in-memory, comprising:
- an N-row receive path, each receive path row including one Digital-to-Analog Converter (DAC) and multiple memory elements;
- an M-column transmit path coupled to the receive path in a mesh structure, wherein each transmit path column consists of one Analog-to-Digital Converter (ADC) and multiple memory elements;
- and
- a single-end current steering Digital-to-Analog Converter (DAC) and a resistor load to convert the input data to voltage output, wherein the voltage output is coupled to a buffer to drive multiple memory elements.
1 more element
A method of data conversion for computing-in-memory, comprising:
- forming an N-row receive path and an M-column transmit path;
- coupling the paths in a mesh structure;
- converting each receive path row with one DAC and multiple memory elements;
- converting the input with a single-end current steering Digital-to-Analog Converter (DAC) and a resistor load to convert the input data to voltage output, wherein the voltage output is coupled to a buffer to drive multiple memory elements;
- and
- digitizing each transmit path column having one ADC and multiple memory elements.
3 more elements
A data converter for computing-in-memory, comprising:
- an N-row receive path, each receive path row including one Digital-to-Analog Converter (DAC) and multiple memory elements;
- and
- an M-column transmit path coupled to the receive path in a mesh structure, wherein each transmit path column consists of one Analog-to-Digital Converter (ADC) and multiple memory elements, wherein the transmit path comprises a trans-impedance amplifier (TIA) and a Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC), wherein input current is coupled to TIA to produce output voltage and an output voltage is sampled by the SAR ADC to yield output data.
Dependencies are inferred from the claim text.