Method of operating analog-to-digital converter by reversed switching technique and analog-to-digital converter utilizing same

A method of operating an analog-to-digital converter, the analog-to-digital converter comprising a first capacitor array, a first selection circuit, a second capacitor array, a second selection circuit, a comparator and a control logic circuit, the first capacitor array comprising a plurality of sets of capacitors, each set of capacitors in the first capacitor array comprising a first capacitor and a second capacitor, the second capacitor array comprising a plurality of sets of capacitors, each set of capacitors in the second capacitor array comprising a first capacitor and a second capacitor, the first selection circuit being coupled to the first capacitor array, the second selection circuit being coupled to the second capacitor array, the comparator comprising a first input terminal coupled to the first capacitor array, and a second input terminal coupled to the second capacitor array, the control logic circuit being coupled to the first selection circuit, the second selection circuit, and the comparator, the method comprising:

• in a first sampling period, the first selection circuit outputting a first reference voltage to the first capacitor in each set of capacitors in the first capacitor array and output a second reference voltage to the second capacitor in each set of capacitors in the first capacitor array, and the second selection circuit outputting the first reference voltage to the first capacitor in each set of capacitors in the second capacitor array and output the second reference voltage to the second capacitor in each set of capacitors in the second capacitor array;
• in a first conversion period, the comparator comparing a voltage at the first input terminal and a voltage at the second input terminal to generate a first comparison result, the first selection circuit outputting the second reference voltage to a first capacitor of a set of larger capacitors in the first capacitor array, and the second selection circuit outputting the first reference voltage to a second capacitor of a set of larger capacitors in the second capacitor array;
• and
• in a second conversion period subsequent to the first conversion period, the comparator comparing a voltage at the first input terminal and a voltage at the second input terminal to generate a second comparison result, the first selection circuit outputting the first reference voltage to a first capacitor portion of the first capacitor of the set of larger capacitors in the first capacitor array or a first capacitor portion of a second capacitor of the set of larger capacitors in the first capacitor array, and the second selection circuit outputting the second reference voltage to a first capacitor portion of a first capacitor of the set of larger capacitors in the second capacitor array or a first capacitor portion of the second capacitor of the set of larger capacitors in the second capacitor array;
• wherein the first comparison result and the second comparison result are different.