Method and system for providing word addressable nonvolatile memory in a programmable logic device

A method of configuring a field programmable gate array (“FPGA”) containing nonvolatile memory (“NVM”) comprising:

• dividing a nonvolatile memory (“NVM”) into a configuration NVM storage and a user NVM storage;
• organizing the user NVM storage into an array of word-wide memory storage accessible by a memory address operable as random memory access;
• receiving configuration data representing user desirable logic functions for programming at least a portion of the FPGA from a configuration NVM of a NVM storage in the FPGA;
• identifying a plurality of NVM bits in one or more lookup tables (“LUTs”) within configurable LBs of the FPGA in accordance with the configuration data;
• programming logic values to the plurality of NVM bits of the LUTs in response to the configuration data;
• and
• facilitating the configurable LBs of the FPGA to carry out the user desirable logic functions based on the logic values in the plurality of NVM bits of the LUTs.

A field programmable gate array (“FPGA”) containing lookup tables (“LUTs”), comprising:

• a programmable interconnection array (“PIA”) containing multiple internal buses configured to selectively route information between logic components and input/output ports based on configuration data;
• a nonvolatile memory (“NVM”) coupled to the PIA and configured to be flexibly organized to include a configuration NVM storage for storing the configuration data and a user NVM storage, wherein the user NVM storage is organized in an array of word-wide memory storage accessible by a memory address operable as random memory access;
• and
• a first LUT of multiple LUTs in FPGA, coupled to the PIA, containing a plurality of ferroelectric random-access memory (“FeRAM”) bits in the first LUT able to persistently store configuration information for configuring the first LUT in response to the configuration data.