Device and method for enhancing voltage regulation performance

A device for buffering a reference signal comprising:

• a regulator circuit having an input configured to be in electrical communication with the reference signal and having at least two outputs, wherein the regulator circuit is configured to generate at least two replicas of the reference signal as regulated output signals and to respectively output the at least two replicas of the reference signal via the at least two outputs and wherein the regulator circuit comprises a plurality of regulator sub-blocks, wherein each regulator sub-block is configured to generate a respective regulated output signal;
• and
• wherein each regulator sub-block comprises a clocked comparator, a charge reservoir, a charge source/sink circuitry and a variable resistor, wherein the clocked comparator is configured to compare the regulated output signal to the reference signal, and the regulator sub-block is further configured to perform charge sharing operation between the charge reservoir and the charge source/sink circuitry, and wherein the variable resistor is configured to define one or both of:
• charging and discharging of the charge reservoir;
• wherein the regulator circuit is further configured to receive a plurality of reference signals and wherein the regulator circuit is configured to generate at least two replicas of all or some of the reference signals as regulated output signals;
• a receiving circuit having at least two inputs in electrical communication with the at least two outputs of the regulator circuit and a switch circuit configured to electrically couple one of the at least two inputs to further circuitry of the receiving circuit wherein the switching circuit is configured to switch from one regulated output signal to another regulated output signal in a non-overlapping manner,
• wherein the receiving circuit further comprises a detector circuit configured to provide control signals to the switching circuit to control the switching circuit to switch from one regulated output signal to another regulated output signal at a time at which a desired performance characteristic of the regulated output signal changes, and wherein the detector circuit is further configured to sense a delayed version of a trigger signal at which the receiving circuit starts operation;
• and
• wherein the regulated output signals are configured to have with different performance characteristics.