Clock selector circuit

A clock selector circuit comprising:

• a first input for receiving a reference clock signal having a reference frequency;
• a second input for receiving an offset clock signal having an offset frequency, wherein the offset frequency differs from the reference frequency by a frequency offset;
• a clock output for outputting the reference clock signal or the offset clock signal as an output clock signal;
• and
• switching circuitry,
• wherein the switching circuitry comprises a switching input and is arranged, when the clock selector circuit is outputting a current one of the reference and offset clock signals as the output clock signal, in response to receiving a switching signal at the switching input indicating that the output clock signal should be switched to be a new one of the reference and offset clock signals, to detect when like edges of the reference clock signal and the offset clock signal are aligned to within a predetermined tolerance with the new clock signal leading the current clock signal in phase, if the offset frequency is lower than the reference frequency, or with the new clock signal trailing the current clock signal in phase, if the offset frequency is higher than the reference frequency, and, in response to said detection, to switch to outputting the new clock signal from the clock output.