Voltage tolerant oscillator with enhanced RF immunity performance
AssigneeTexas Instruments Incorporated
InventorsSumantra Seth, Isha Khandelwal, Rama Santosh Neelim Kumar Kattamuri
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Abstract
An integrated circuit includes an inverter, first and second capacitors, a resistor, and a transistor. The inverter has an input and an output. The first capacitor is coupled to a ground. The transistor has a first transistor terminal, a second transistor terminal, and a control input. The first transistor terminal is coupled to the first capacitor and the second transistor terminal is coupled to the input of the inverter. The second capacitor is coupled between the output of the inverter and the ground. The resistor is coupled between the output of the inverter and the first transistor terminal.
Claims15
An integrated circuit, comprising:
- an inverter having an input and an output;
- a first capacitor coupled to a ground;
- a transistor having a first transistor terminal, a second transistor terminal, and a control input, the first transistor terminal coupled to the first capacitor and the second transistor terminal coupled to the input of the inverter;
- a second capacitor coupled between the output of the inverter and the ground;
- a resistor coupled between the output of the inverter and the first transistor terminal;
- an input/output (I/O) pin;
- and
- a notch filter coupled between the I/O pin and the first transistor terminal.
A circuit, comprising:
- an inverter having an input and an output;
- a buffer having an input coupled to the output of the inverter;
- a first capacitor coupled to a ground;
- a transistor having a first transistor terminal, a second transistor terminal, and a control input, the first transistor terminal coupled to the first capacitor and the second transistor terminal coupled to the input of the inverter;
- a second capacitor coupled between the output of the inverter and the ground;
- a resistor coupled between the output of the inverter and the first transistor terminal;
- a first input/output (I/O) pin coupled to the first transistor terminal, the first I/O pin adapted to be coupled to a clock generator;
- a second I/O pin coupled to the output of the inverter, the second I/O pin adapted to be coupled to a crystal;
- and
- a third I/O pin coupled to the first transistor terminal, the third I/O pin adapted to be coupled to the crystal.
A system comprising:
- a processing unit media access controller (MAC);
- an automotive connector;
- a clock source;
- and
- an Ethernet physical interface (PHY) transceiver integrated circuit (IC) coupled to the processing unit MAC, to the automotive connector, and to the clock source, the Ethernet PHY transceiver IC comprising:
- a first input/output (I/O) pin coupled to the clock source;
- a second I/O pin adapted to be coupled to a crystal;
- a third I/O pin adapted to be coupled to the crystal;
- an inverter having an inverter input and an inverter output, the inverter output coupled to the second I/O pin;
- a first capacitor having a first capacitor terminal and a second capacitor terminal, the second capacitor terminal coupled to a ground terminal;
- a transistor having a first current terminal, a second current terminal, and a control terminal, the first current terminal coupled to the first capacitor terminal, to the first I/O pin, and to the third I/O pin, and the second current terminal coupled to the inverter input;
- a second capacitor having a third capacitor terminal and a fourth capacitor terminal, the third capacitor terminal coupled to the inverter output and the fourth capacitor terminal coupled to the ground terminal;
- and
- a resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal coupled to the first current terminal and the second resistor terminal coupled to the inverter output.
Dependencies are inferred from the claim text.