Peak detection for current mode control in a power converter system

A power converter system comprising:

• a transistor;
• a driver configured to activate or deactivate the transistor;
• and
• a controller comprising:
• a first circuit configured to generate an error current based on a difference between a reference signal and a feedback signal, wherein the feedback signal depends on an output voltage of the power converter system;
• a frequency generator configured to generate an activation signal based on the difference between the reference signal and the feedback signal;
• a pedestal circuit configured to define a peak current threshold for the transistor based on an offset value;
• and
• a logic circuit configured to:
• cause the driver to activate the transistor based on the activation signal;
• and
• cause the driver to deactivate the transistor when a current sense signal reaches the defined peak current threshold, wherein the current sense signal is representative of a power current conducted by the transistor,
• wherein the controller further comprises:
• a peak detection comparator comprising a first input node and a second input node;
• a current sense circuit coupled to the first input node;
• and
• a reference current source coupled to the second input node,
• wherein the first circuit is coupled to the first input node,
• wherein the pedestal circuit is coupled to the first input node, and
• wherein the peak detection comparator is configured to cause the driver to deactivate the transistor in response to comparing current amplitudes at the first and second input nodes.

A method for controlling a transistor in a power converter system, the method comprising:

• generating, by an amplifier of a controller, an error current based on a difference between a reference signal and a feedback signal, wherein the feedback signal depends on an output voltage of the power converter system;
• generating, by a frequency generator of the controller, an activation signal based on the difference between the reference signal and the feedback signal;
• defining, by a pedestal circuit of the controller, a peak current threshold for the transistor based on an offset value;
• activating, by a logic circuit of the controller, the transistor based on the activation signal;
• and
• deactivating, by the logic circuit, the transistor when a current sense signal reaches the defined peak current threshold, wherein the current sense signal is representative of a power current conducted by the transistor,
• wherein the transistor is a high-side switch in a direct current/direct current (DC/DC) converter, and
• wherein the DC/DC converter is configured to deliver three milliamperes to a load at an efficiency of greater than eighty-one percent.

A device for controlling a transistor in a power converter system, the device comprising:

• a first circuit configured to generate an error current based on a difference between a reference signal and a feedback signal, wherein the feedback signal depends on an output voltage of the power converter system;
• a frequency generator configured to generate an activation signal based on the difference between the reference signal and the feedback signal;
• a pedestal circuit configured to define a peak current threshold for the transistor based on an offset value;
• and
• a logic circuit configured to:
• activate the transistor based on the activation signal;
• and
• deactivate the transistor when a current sense signal reaches the defined peak current threshold, wherein the current sense signal is representative of a power current conducted by the transistor,
• wherein the device further comprises:
• a peak detection comparator comprising a first input node and a second input node;
• a current sense circuit coupled to the first input node;
• and
• a reference current source coupled to the second input node,
• wherein the first circuit is coupled to the first input node,
• wherein the pedestal circuit is coupled to the first input node,
• wherein the peak detection comparator is configured to cause the logic circuit to deactivate the transistor in response to comparing current amplitudes at the first and second input nodes.

A device for controlling a transistor in a power converter system, the device comprising:

• a first circuit configured to generate an error current based on a difference between a reference signal and a feedback signal, wherein the feedback signal depends on an output voltage of the power converter system;
• a frequency generator configured to generate an activation signal based on the difference between the reference signal and the feedback signal;
• a pedestal circuit configured to define a peak current threshold for the transistor based on an offset value;
• and
• a logic circuit configured to:
• activate the transistor based on the activation signal;
• and
• deactivate the transistor when a current sense signal reaches the defined peak current threshold, wherein the current sense signal is representative of a power current conducted by the transistor,
• wherein the pedestal circuit comprises a current mirror configured to generate the offset value as a pedestal current,
• wherein the pedestal circuit further comprises a resistor, and
• wherein the current mirror is configured to generate the pedestal current based on a fourth current through the resistor.